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Part Number S5935 Revision 1.02 - June 27, 2006
S5935
PCI Product
Data Book
S5935
PCI PRODUCT DATA BOOK
AMCC Confidential and Proprietary
DS1527
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S5935 - PCI Product
Revision 1.02 - June 27, 2006
Data Book
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DS1527
AMCC Confidential and Proprietary
Part Number S5935 Revision 1.02 - June 27, 2006
S5935
PCI Product
FEATURES
* * * * * * * * * * * * * * PCI 2.1 Compliant Master/Slave Device Full 132 Mbytes/sec Transfer Rate Supports new Intel 440BX/GX Chipsets Supports new WinNT Service Pack 2 & 3 PCI Bus Operation DC to 33 MHz 8/16/32 Bit Add-On User Bus Four Definable Pass-Thru Data Channels Two 32 Byte Internal FIFOs w/DMA Synchronous Add-On Bus Operation Mail Box Registers w/Byte Level Status Direct Mail Box Data Strobe/Interrupts Direct PCI & Add-On Interrupt Pins Optional Non-Volatile Memory Boot Loading Optional Expansion BIOS/POST Code
Data Book
DESCRIPTION
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system's processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry's need for a bus standard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video. Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed the S5935 to solve the problem of interfacing applications to the PCI Local bus while offering support for newer PCI chipsets and operating systems. The S5935 is a powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can serve simply as a PCI bus Target with modest transfer requirements. For high-performance applications, the S5935 can become a Bus Master to attain the PCI Local bus peak transfer capability of 132 MBytes/sec. The S5935 PCI controller also maintains dropin compatibility for upgrading many existent S5933 designs requiring migration into new motherboard architectures, PCI BIOSs and software operating systems.
APPLICATIONS
* * * * * * * * * * * High Speed Networking Digital Video Applications I/O Communications Ports High Speed Data Input/Output Multimedia Communications Memory Interfaces High Speed Data Acquisition Data Encryption/Decryption Intel i960 Interface General Purpose PCI Interfacing Existent S5933 Design Upgrades
Figure 1. S5935 Block Diagram
S5935
Pass-Thru Data & Address Registers 2.1 PCI Local Bus Interface Logic Mux/Demux FIFOs Buffers Mailboxes Read/W rite Control Configuration Registers Status Registers Mux/Demux Buffers
Proprietary Backplane Satellite Receiver/ Modem User Application I/O Audio ISDN FDDI ATM Graphics/ MPEG/ Grabber
PCI Local Bus
Bus MasterTransfer Count &Address Registers
AMCC Add-On Local Bus Interface Logic
Serial/Parallel nvRAM Configuration Space Expansion BIOS
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TABLE OF CONTENTS
FEATURES .............................................................................................................................................................. 3 APPLICATIONS ...................................................................................................................................................... 3 DESCRIPTION ........................................................................................................................................................ 3 TABLE OF CONTENTS .......................................................................................................................................... 4 LIST OF FIGURES .................................................................................................................................................. 9 LIST OF TABLES .................................................................................................................................................. 12 S5935 ARCHITECTURE ....................................................................................................................................... 14 S5935 Register Architecture ............................................................................................................................ 14 PCI Configuration Registers ............................................................................................................................ 15 PCI Operation Registers .................................................................................................................................. 15 Add-On Bus Operation Registers .................................................................................................................... 16 Non-Volatile Memory Interface ........................................................................................................................ 16 Mailbox Operation ........................................................................................................................................... 17 Pass-Thru Operation ....................................................................................................................................... 19 FIFO PCI Bus Mastering Operation ................................................................................................................. 19 Signal Type Definition ...................................................................................................................................... 23 NON-VOLATILE MEMORY INTERFACE SIGNALS ............................................................................................ 27 ADD-ON BUS INTERFACE SIGNALS .................................................................................................................. 28 PCI CONFIGURATION REGISTERS .................................................................................................................... 32 VENDOR IDENTIFICATION REGISTER (VID) ..................................................................................................... 34 DEVICE IDENTIFICATION REGISTER (DID) ....................................................................................................... 35 PCI COMMAND REGISTER (PCICMD) ................................................................................................................ 36 PCI STATUS REGISTER (PCISTS) ...................................................................................................................... 38 REVISION IDENTIFICATION REGISTER (RID) ................................................................................................... 40 CLASS CODE REGISTER (CLCD) ....................................................................................................................... 41 CACHE LINE SIZE REGISTER (CALN) ............................................................................................................... 45 LATENCY TIMER REGISTER (LAT) .................................................................................................................... 46 HEADER TYPE REGISTER (HDR) ....................................................................................................................... 47 BUILT-IN SELF-TEST REGISTER (BIST) ............................................................................................................ 48 BASE ADDRESS REGISTERS (BADR) ............................................................................................................... 49 Determining Base Address Size ...................................................................................................................... 49 Assigning the Base Address ............................................................................................................................ 49 EXPANSION ROM BASE ADDRESS REGISTER (XROM) ................................................................................. 53 INTERRUPT LINE REGISTER (INTLN) ................................................................................................................ 55 INTERRUPT PIN REGISTER (INTPIN) ................................................................................................................. 56 MINIMUM GRANT REGISTER (MINGNT) ............................................................................................................ 57 MAXIMUM LATENCY REGISTER (MAXLAT) ...................................................................................................... 58 OUTGOING MAILBOX REGISTERS (OMB) ........................................................................................................ 61 INCOMING MAILBOX REGISTERS (IMB) ........................................................................................................... 61 FIFO REGISTER PORT (FIFO) ............................................................................................................................. 61 PCI CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR) ..................................................... 62
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PCI CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) ..................................... 63 PCI CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) ....................................................... 64 PCI CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) ........................................ 65 MAILBOX EMPTY FULL/STATUS REGISTER (MBEF) ....................................................................................... 66 INTERRUPT CONTROL/STATUS REGISTER (INTCSR) .................................................................................... 68 MASTER CONTROL/STATUS REGISTER (MCSR) ............................................................................................ 72 ADD-ON BUS OPERATION REGISTERS ............................................................................................................ 76 ADD-ON INCOMING MAILBOX REGISTERS (AIMBX) ....................................................................................... 77 ADD-ON OUTGOING MAILBOX REGISTERS (AOMBX) .................................................................................... 77 ADD-ON FIFO REGISTER PORT (AFIFO) ........................................................................................................... 77 ADD-ON CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR) ............................................ 78 ADD-ON PASS-THRU ADDRESS REGISTER (APTA) ........................................................................................ 79 ADD-ON PASS-THRU DATA REGISTER (APTD) ............................................................................................... 79 ADD-ON CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) ............................................... 80 ADD-ON EMPTY/FULL STATUS REGISTER (AMBEF) ...................................................................................... 81 ADD-ON INTERRUPT CONTROL/STATUS REGISTER (AINT) .......................................................................... 83 ADD-ON GENERAL CONTROL/STATUS REGISTER (AGCSTS) ...................................................................... 86 ADD-ON CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) ............................. 89 ADD-ON CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) ............................... 90 INITIALIZATION .................................................................................................................................................... 92 PCI RESET ............................................................................................................................................................ 92 LOADING FROM BYTE-WIDE NV MEMORIES ................................................................................................... 92 PCI BUS CONFIGURATION CYCLES .................................................................................................................. 95 EXPANSION BIOS ROMS .................................................................................................................................... 97 PCI BUS INTERFACE ......................................................................................................................................... 100 PCI BUS TRANSACTIONS ................................................................................................................................. 100 PCI BURST TRANSFERS ................................................................................................................................... 102 PCI Read Transfers ....................................................................................................................................... 102 PCI Write Transfers ....................................................................................................................................... 104 Master-Initiated Termination .......................................................................................................................... 105 Normal Cycle Completion .............................................................................................................................. 105 Initiator Preemption ....................................................................................................................................... 106 Master Abort .................................................................................................................................................. 107 Target-Initiated Termination .......................................................................................................................... 107 Target Disconnects ........................................................................................................................................ 108 Target Requested Retries ............................................................................................................................. 109 Target Aborts ................................................................................................................................................. 109 PCI BUS MASTERSHIP ...................................................................................................................................... 111 Bus Mastership Latency Components ........................................................................................................... 111 Bus Arbitration ............................................................................................................................................... 111 Bus Acquisition .............................................................................................................................................. 112 Target Latency ............................................................................................................................................... 112 Target Locking ............................................................................................................................................... 112
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PCI BUS INTERRUPTS ...................................................................................................................................... 114 PCI BUS PARITY ERRORS ................................................................................................................................ 114 ADD-ON BUS INTERFACE ................................................................................................................................. 116 ADD-ON OPERATION REGISTER ACCESSES ................................................................................................ 116 Add-On Interface Signals .............................................................................................................................. 116 System Signals .............................................................................................................................................. 116 Register Access Signals ................................................................................................................................ 116 Asynchronous Register Accesses ................................................................................................................. 117 Synchronous FIFO and Pass-Thru Data Register Accesses ........................................................................ 117 nv Memory Accesses Through the Add-On General Control/Status Register ............................................... 117 MAILBOX BUS INTERFACE .............................................................................................................................. 117 Mailbox Interrupts .......................................................................................................................................... 120 FIFO BUS INTERFACE ....................................................................................................................................... 120 FIFO Direct Access Inputs ............................................................................................................................. 120 FIFO Status Signals ...................................................................................................................................... 120 FIFO Control Signals ..................................................................................................................................... 120 PASS-THRU BUS INTERFACE .......................................................................................................................... 120 Pass-Thru Status Indicators .......................................................................................................................... 120 Pass-Thru Control Inputs ............................................................................................................................... 120 NON-VOLATILE MEMORY INTERFACE ........................................................................................................... 121 Non-Volatile Memory Interface Signals ......................................................................................................... 121 Accessing Non-Volatile Memory .................................................................................................................... 121 nv Memory Device Timing Requirements ...................................................................................................... 124 MAILBOX OVERVIEW ........................................................................................................................................ 126 FUNCTIONAL DESCRIPTION ............................................................................................................................ 126 Mailbox Empty/Full Conditions ...................................................................................................................... 127 Mailbox Interrupts .......................................................................................................................................... 127 Add-On Outgoing Mailbox 4, Byte 3 Access ................................................................................................. 127 BUS INTERFACE ................................................................................................................................................ 128 PCI Bus Interface .......................................................................................................................................... 128 Add-On Bus Interface .................................................................................................................................... 128 8-Bit and 16-Bit Add-On Interfaces ................................................................................................................ 128 CONFIGURATION ............................................................................................................................................... 129 Mailbox Status ............................................................................................................................................... 129 Mailbox Interrupts .......................................................................................................................................... 130 FIFO OVERVIEW ................................................................................................................................................ 134 FUNCTIONAL DESCRIPTION ............................................................................................................................ 134 FIFO Buffer Management and Endian Conversion ....................................................................................... 134 FIFO Advance Conditions ............................................................................................................................. 134 Endian Conversion ........................................................................................................................................ 135 64-Bit Endian Conversion .............................................................................................................................. 136 Add-On FIFO Status Indicators ..................................................................................................................... 137 Add-On FIFO Control Signals ........................................................................................................................ 137 PCI Bus Mastering with the FIFO .................................................................................................................. 137 Add-On Initiated Bus Mastering ..................................................................................................................... 137
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PCI Initiated Bus Mastering ........................................................................................................................... 138 Address and Transfer Count Registers ......................................................................................................... 138 Bus Mastering FIFO Management Schemes ................................................................................................ 138 FIFO Bus Master Cycle Priority ..................................................................................................................... 139 FIFO Generated Bus Master Interrupts ......................................................................................................... 139 BUS INTERFACE ................................................................................................................................................ 139 FIFO PCI Interface (Target Mode) ................................................................................................................. 139 FIFO PCI Interface (Initiator Mode) ............................................................................................................... 140 FIFO PCI Bus Master Reads ......................................................................................................................... 142 FIFO PCI Bus Master Writes ......................................................................................................................... 142 Add-On Bus Interface .................................................................................................................................... 142 Add-On FIFO Register Accesses .................................................................................................................. 142 Add-On FIFO Direct Access Mode ................................................................................................................ 142 Additional Status/Control Signals for Add-On Initiated Bus Mastering .......................................................... 144 FIFO Generated Add-On Interrupts ............................................................................................................... 145 8-Bit and 16-Bit FIFO Add-On Interfaces ...................................................................................................... 145 CONFIGURATION ............................................................................................................................................... 146 FIFO Setup During Initialization ..................................................................................................................... 146 FIFO Status and Control Bits ......................................................................................................................... 146 PCI Initiated FIFO Bus Mastering Setup ....................................................................................................... 147 PASS-THRU OVERVIEW .................................................................................................................................... 149 FUNCTIONAL DESCRIPTION ............................................................................................................................ 149 Pass-Thru Transfers ...................................................................................................................................... 150 Pass-Thru Status/Control Signals ................................................................................................................. 151 Pass-Thru Add-On Data Bus Sizing .............................................................................................................. 151 BUS INTERFACE ................................................................................................................................................ 151 PCI Bus Interface .......................................................................................................................................... 151 PCI Pass-Thru Single Cycle Accesses .......................................................................................................... 151 PCI Pass-Thru Burst Accesses ..................................................................................................................... 152 PCI Retry Conditions ..................................................................................................................................... 152 PCI Write Retries ........................................................................................................................................... 152 PCI Read Retries ........................................................................................................................................... 153 Add-On Bus Interface .................................................................................................................................... 153 Single Cycle Pass-Thru Writes ...................................................................................................................... 153 Single Cycle Pass-Thru Reads ...................................................................................................................... 156 Pass-Thru Burst Writes ................................................................................................................................. 156 Pass-Thru Burst Reads ................................................................................................................................. 161 Add-On Pass-Thru Disconnect Operation ..................................................................................................... 165 8-Bit and 16-Bit Pass-Thru Add-On Bus Interface ......................................................................................... 166 CONFIGURATION ............................................................................................................................................... 170 S5935 Base Address Register Definition ...................................................................................................... 170 Creating a Pass-Thru Region ........................................................................................................................ 170 Accessing a Pass-Thru Region ..................................................................................................................... 171 ABSOLUTE MAXIMUM RATINGS ...................................................................................................................... 173 DC CHARACTERISTICS ..................................................................................................................................... 173
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PCI BUS SIGNALS ............................................................................................................................................. 174 ADD-ON BUS SIGNALS ..................................................................................................................................... 175 AC CHARACTERISTICS ..................................................................................................................................... 176 PCI Bus Timings ............................................................................................................................................ 176 ADD-ON BUS TIMINGS ...................................................................................................................................... 178 Synchronous RDFIFO# Timing ..................................................................................................................... 179 Synchronous WRFIFO# Timing ..................................................................................................................... 180 Asynchronous RD# Register Access Timing ................................................................................................. 181 Asynchronous WR# Register Access Timing ................................................................................................ 182 Synchronous RD# FIFO Timing .................................................................................................................... 183 Synchronous Multiple RD# FIFO Timing ....................................................................................................... 184 Synchronous WR# FIFO Timing .................................................................................................................... 185 Synchronous Multiple WR# FIFO Timing ...................................................................................................... 186 Target S5935 Pass-Thru Interface Timings ................................................................................................... 187 Target Byte-Wide nv Memory Interface Timings ........................................................................................... 189 Target Interrupt Timings ................................................................................................................................ 191 S5935 Pinout and Pin Assignment - 160 PQFP ............................................................................................ 193 S5935 Pinout and Pin Assignment - 208 TQFP ............................................................................................ 194 S5935 Numerical Pin Assignment - 160 PQFP ............................................................................................. 195 Package Physical Dimensions - 160 PQFP .................................................................................................. 197 DOCUMENT REVISION HISTORY ..................................................................................................................... 203 Ordering Information ...................................................................................................................................... 204
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LIST OF FIGURES
Figure 1. S5935 Block Diagram ............................................................................................................................... 3 Figure 2. ................................................................................................................................................................ 14 Figure 3. ................................................................................................................................................................ 18 Figure 4. ................................................................................................................................................................ 19 Figure 5. ................................................................................................................................................................ 20 Figure 6. S5933 Pin Assignment ........................................................................................................................... 21 Figure 7. S5935 Signal Pins .................................................................................................................................. 23 Figure 8. Vendor Identification Register ................................................................................................................. 34 Figure 9. Device Identification Register ................................................................................................................. 35 Figure 10. PCI Command Register ........................................................................................................................ 36 Figure 11. PCI Status Register .............................................................................................................................. 38 Figure 12. Revision Identification Register ............................................................................................................ 40 Figure 13. .............................................................................................................................................................. 41 Figure 14. Cache Line Size Register ..................................................................................................................... 45 Figure 15. Latency Timer Register ......................................................................................................................... 46 Figure 16. Header Type Register ........................................................................................................................... 47 Figure 17. Built-In Self Test Register ..................................................................................................................... 48 Figure 18. Base Address Register -- Memory ....................................................................................................... 49 Figure 19. Expansion ROM Base Address Register .............................................................................................. 53 Figure 20. Interrupt Line Register .......................................................................................................................... 55 Figure 21. Interrupt Pin Register ............................................................................................................................ 56 Figure 22. Minimum Grant Register ....................................................................................................................... 57 Figure 23. Maximum Latency Register .................................................................................................................. 58 Figure 24. PCI Controlled Bus Master Write Address Register ............................................................................. 62 Figure 25. PCI Controlled Bus Master Write Transfer Count Register ................................................................... 63 Figure 26. PCI Controlled Bus Master Read Address Register ............................................................................. 64 Figure 27. PCI Controlled Bus Master Read Transfer Count Register .................................................................. 65 Figure 28. Mailbox Empty/Full Status Register ...................................................................................................... 66 Figure 29. Interrupt Control/Status Register .......................................................................................................... 68 Figure 30. FIFO Management and Endian Control Byte ........................................................................................ 69 Figure 31. Bus Master Control/Status Register ..................................................................................................... 72 Figure 32. Add-On Controlled Bus Master Write Address Register ....................................................................... 78 Figure 33. Add-On Controlled Bus Master Read Address Register ....................................................................... 80 Figure 34. Add-On Mailbox Empty/Full Status Register ......................................................................................... 81 Figure 35. Add-On Interrupt Control/Status Register ............................................................................................. 83 Figure 36. Add-On General Control/Status Register ............................................................................................. 86 Figure 37. Add-On Controlled Bus Master Write Transfer Count Register ............................................................ 89 Figure 38. Add-On Controlled Bus Master Read Transfer Count Register ............................................................ 90 Figure 39. Serial Interface Definition of Start and Stop .......................................................................................... 94 Figure 40. Serial Interface Clock/Data Relationship .............................................................................................. 94
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Figure 41. Serial Interface Byte Access -- Write ................................................................................................... 94 Figure 42. Serial Interface Byte Access -- Read ................................................................................................... 94 Figure 43. PCI AD Bus Definition During a Type 0 Configuration Access ............................................................. 95 Figure 44. Type 0 Configuration Read Cycles ....................................................................................................... 96 Figure 45. Type 0 Configuration Write Cycles ....................................................................................................... 96 Figure 46. Zero Wait State Burst Read PCI Bus Transfer (S5935 as Initiator) .................................................... 102 Figure 47. Single Data Phase PCI Bus Read of S5935 Registers (S5935 as Target) ......................................... 103 Figure 48. Burst PCI Bus Read Attempt to S5935 Registers (S5935 as Target) ................................................. 103 Figure 49. Zero Wait State Burst Write PCI Bus Transfer (S5935 as Initiator) .................................................... 104 Figure 50. Single Data Phase PCI Bus Write of S5935 Registers (S5935 as Target) ......................................... 105 Figure 51. Master-Initiated, Normal Completion (S5935 as either Target or Initiator) ......................................... 105 Figure 52. Master Initiated Termination Due to Preemption and Latency Timer Active (S5935 as Master) ........ 106 Figure 53. Master Initiated Termination Due to Preemption and Latency Timer Expired (S5935 as Master) ...... 106 Figure 54. Master Abort, No Response ............................................................................................................... 107 Figure 55. Target Disconnect Example 1 (IRDY# deasserted) ............................................................................ 108 Figure 56. Target-Initiated Retry .......................................................................................................................... 109 Figure 57. Target Abort Example ......................................................................................................................... 110 Figure 58. PCI Bus Arbitration and S5935 Bus Ownership Example ................................................................... 110 Figure 59. PCI Bus Access Latency Components ............................................................................................... 111 Figure 60. Engaging the LOCK# Signal ............................................................................................................... 112 Figure 61. Access to a Locked Target by its Owner ............................................................................................ 113 Figure 62. Access Attempt to a Locked Target .................................................................................................... 113 Figure 63. Error Reporting Signals ...................................................................................................................... 115 Figure 64. Asynchronous Add-On Operation Register Read ............................................................................... 118 Figure 65. Asynchronous Add-On Operation Register Write ............................................................................... 118 Figure 66. Synchronous FIFO or Pass-Thru Data Register Read ....................................................................... 119 Figure 67. Synchronous FIFO or Pass-Thru Data Register Write ........................................................................ 119 Figure 68. nv Memory Read Operation ................................................................................................................ 124 Figure 69. nv Memory Write Operation ................................................................................................................ 125 Figure 70. Block Diagram - PCI to Add-On Mailbox Register .............................................................................. 126 Figure 71. Block Diagram - Add-On to PCI Mailbox Register .............................................................................. 126 Figure 72. INTCSR FIFO Advance and Endian Control Bits ................................................................................ 134 Figure 73. Figure 2a. 16-bit Endian Conversion .................................................................................................. 135 Figure 74. PCI Read from a Full S5935 FIFO ...................................................................................................... 140 Figure 75. PCI Read from an Empty S5935 FIFO (Target Disconnect) ............................................................... 140 Figure 76. PCI Write to an Empty S5935 FIFO .................................................................................................... 141 Figure 77. PCI Write to a Full S5935 FIFO (Target Disconnect) .......................................................................... 141 Figure 78. Synchronous FIFO Register Burst Read Access Example ................................................................. 143 Figure 79. Synchronous FIFO Register Burst RDFIFO# Access Example .......................................................... 144 Figure 80. Single Cycle Pass-Thru Write ............................................................................................................. 153 Figure 81. Single Cycle Pass-Thru Write with PTADR# ...................................................................................... 154
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Figure 82. Single Cycle Pass-Thru Read with PTADR# ...................................................................................... 158 Figure 83. Pass-Thru Burst Write ........................................................................................................................ 158 Figure 84. Pass-Thru Burst Writes Controlled by PTRDY# ................................................................................. 159 Figure 85. Pass-Thru Burst Read ........................................................................................................................ 161 Figure 86. PCI Burst Read Controlled by PTRDY# .............................................................................................. 163 Figure 87. Target Requested Retry on the First PCI Data Phase ........................................................................ 165 Figure 88. Target Requested Retry after the First Data Phase of a Burst Operation .......................................... 166 Figure 89. Pass-Thru Signals after a Target Requested Retry ............................................................................ 167 Figure 90. Pass-Thru Write to an 8-bit Add-On Device ........................................................................................ 169 Figure 91. PCI Clock Timing ................................................................................................................................ 176 Figure 92. PCI Output Timing .............................................................................................................................. 177 Figure 93. PCI Input Timing ................................................................................................................................. 177 Figure 94. Add-On Clock Timing .......................................................................................................................... 178 Figure 95. Pass-Thru Clock Relationship to PCI Clock ........................................................................................ 178 Figure 96. Synchronous RDFIFO# Timing ........................................................................................................... 179 Figure 97. Synchronous WRFIFO# Timing .......................................................................................................... 180 Figure 98. Asynchronous RD# FIFO Timing ........................................................................................................ 181 Figure 99. Asynchronous WR# FIFO Timing ....................................................................................................... 182 Figure 100. Synchronous RD# FIFO Timing ........................................................................................................ 183 Figure 101. Synchronous RD# FIFO Timing ........................................................................................................ 184 Figure 102. Synchronous WR# FIFO Timing ....................................................................................................... 185 Figure 103. Synchronous Multiple WR# FIFO Timing .......................................................................................... 186 Figure 104. Pass-Thru Data Register Read Timing ............................................................................................. 188 Figure 105. Pass-Thru Data Register Write Timing ............................................................................................. 188 Figure 106. Pass-Thru Status Indicator Timing ................................................................................................... 189 Figure 107. nv Memory Read Timing ................................................................................................................... 190 Figure 108. nv Memory Write Timing ................................................................................................................... 190 Figure 109. IRQ# Interrupt Output Timing ........................................................................................................... 191 Figure 110. Mailbox 4, Byte 3 Direct Input Timing ............................................................................................... 191 Figure 111. S5935 - 160 PQFP Package Drawing .............................................................................................. 197 Figure 112. S5935 - Marking Drawing ................................................................................................................. 198 Figure 113. Package Physical Dimension - 208 TQFP ........................................................................................ 202
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LIST OF TABLES
Table 1. PCI Configuration Registers .................................................................................................................... 15 Table 2. PCI Operation Registers .......................................................................................................................... 16 Table 3. Add-On Bus Operation Registers ............................................................................................................ 17 Table 4. Configuration Registers ........................................................................................................................... 32 Table 5. Vendor Identification Register .................................................................................................................. 34 Table 6. Device Identification Register .................................................................................................................. 35 Table 7. PCI Command Register ........................................................................................................................... 37 Table 8. PCI Status Register ................................................................................................................................. 39 Table 9. Revision Identification Register ................................................................................................................ 40 Table 10. Defined Base Class Codes .................................................................................................................... 41 Table 11. Base Class Code 00h: Early, Pre-2.0 Specification Devices ................................................................. 42 Table 12. Base Class Code 01h: Mass Storage Controllers .................................................................................. 42 Table 13. Base Class Code 02h: Network Controllers ........................................................................................... 42 Table 14. Base Class Code 03h: Display Controllers ............................................................................................ 42 Table 15. Base Class Code 04h: Multimedia Devices ........................................................................................... 42 Table 16. Base Class Code 05h: Memory Controllers ........................................................................................... 42 Table 17. Base Class Code 06h: Bridge Devices .................................................................................................. 43 Table 18. Base Class Code 07h: Simple Communications Controllers ................................................................. 43 Table 19. Base Class Code 08h: Base System Peripherals .................................................................................. 43 Table 20. Base Class Code 09h: Input Devices .................................................................................................... 43 Table 21. Base Class Code 0Ah: Docking Stations ............................................................................................... 44 Table 22. Base Class Code 0Bh: Processors ........................................................................................................ 44 Table 23. Base Class Code 0Ch: Serial Bus Controllers ....................................................................................... 44 Table 24. Built-In Self-Test Register ...................................................................................................................... 48 Table 25. Base Address Register -- Memory (Bit 0 = 0) ....................................................................................... 50 Table 26. Read Response (Memory Assigned) to an All-Ones Write Operation to a Base Address Register ...... 51 Table 27. Read Response (I/O Assigned) to an All-Ones write Operation to a Base Address Register ............... 52 Table 28. Expansion ROM Base Address Register ............................................................................................... 53 Table 29. Read Response to Expansion ROM Base Address Register (after all-ones written) ............................. 54 Table 30. Operation Registers -- PCI Bus ............................................................................................................ 60 Table 31. Mailbox Empty/Full Status Register ....................................................................................................... 67 Table 32. Interrupt Control/Status Register ........................................................................................................... 70 Table 33. Bus Master Control/Status Register ....................................................................................................... 73 Table 34. Operation Registers -- Add-On Interface .............................................................................................. 76 Table 35. Add-On Mailbox Empty/Full Status Register .......................................................................................... 82 Table 36. Interrupt Control/Status Register ........................................................................................................... 84 Table 37. Add-On General Control/Status Register ............................................................................................... 87 Table 38. Valid External Boot Memory Contents ................................................................................................... 93 Table 39. PC Compatible Expansion ROM ............................................................................................................ 97 Table 40. PCI Data Structure ................................................................................................................................. 98
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Table 41. Supported PCI Bus Commands ........................................................................................................... 101 Table 42. Target Termination Types .................................................................................................................... 109 Table 43. Possible Combinations of FRAME# and IRDY# .................................................................................. 112 Table 44. Byte Lane Steering for Pass-Thru Data Register Read (PCI Write) .................................................... 168 Table 45. Byte Lane Steering for Pass-Thru Data Register Write (PCI Read) .................................................... 168
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The S5935 is an off-the-shelf, low-cost, standard product, which is PCI 2.1 compliant. And, since AMCC is a member of the PCI Special Interest Group, the S5935 has been tested on various manufacturer's PCI motherboards, chip sets, PCI BIOSs and operating systems. This removes the burden of compliance and compatibility testing from the designer and thus significantly reduces development time. Utilizing the S5935 allows the designer to focus on the actual application, not debugging the PCI interface. The S5935 allows special direct data accessing between the PCI bus and the user application through implementation of four definable Pass-Thru data channels. Each data channel is implemented by defining a Host memory segment size and 8/16/32-bit user bus width. The addition of two 32 byte FIFOs, also used in S5935 Bus Mastering applications, provides further versatility to data transfer capabilities. FIFO DMA transfers are supported using Address and Transfer Count Registers. Four 32-bit Mailbox Registers coupled with a Status Register and extensive interrupt capabilities provide flexible user command or message transfers between the two buses. In addition, the S5935 also allows use of an external serial, or bytewide non-volatile memory to perform any pre-boot initialization requirements and to provide custom expansion BIOS or POST code capability. Local Bus signal are detailed on the right side. All additional S5935 device control signals are shown on the lower right side. The S5935 supports a two wire serial nvRAM bus and a byte-wide EPROM/FLASH bus. This allows the designer to customize the S5935 configuration by loading setup information on system power-up. Figure 2.
PCLK INTA# RST# AD[31:0] C/BE[3:0]# REQ# GNT# FRAME# DEVSEL# IRDY# TRDY# IDSEL# STOP# LOCK# PAR PERR# SERR#
S5935
BPCLK IRQ# SYSRST# DQ[31:0] SELECT# ADR[6:2] BE[3:0]# RD# WR#
Add-On Bus Control Add-On Data Bus S5933 Register Access
PCI Local Bus
PTATN# PTBURST# PTNUM[1:0]# PTBE[3:0]# PTADR# PTWR PTRDY# RDFIFO# WRFIFO# RDEMPTY WRFULL EA[15:0] EQ[7:0] EWR#/SDA ERD#/SCL
Pass-Thru Control/Access
Direct FIFO Access Byte Wide Config/BIOS Opt. Serial Bus Config/BIOS Opt.
S5935 Control
MODE SNV
S5935 ARCHITECTURE
The block diagram in Figure 1 above shows the major functional elements within the S5935. The S5935 provides three physical bus interfaces: the PCI Local bus, the user local bus referred to as the Add-On Local bus and the optional serial and byte-wide non-volatile memory buses. Data movement between buses can take place through mailbox registers or the FIFO data channel, or a user can define and enable one or more of the four Pass-Thru data channels. S5935 Bus Master or DMA data transfers to and from the PCI Local bus are performed through the FIFO data channel under either Host or Add-On software control or AddOn hardware control using dedicated S5935 signal pins. The S5935 signal pins are shown in Figure 2. The PCI Local Bus signals are detailed on the left side; Add-On
S5935 Register Architecture Control and configuration of the Add-On Local bus, and the S5935 itself, is performed through three primary groups of registers. These groups consist of PCI Configuration Registers, PCI Operation Registers and Add-On Operation Registers. These registers are user configurable through either their associated bus or from an external non-volatile memory device. This section will provide a brief overview of each of these register groups and the optional non-volatile interface.
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PCI Configuration Registers All PCI compliant devices are required to provide a group of Configuration Registers for the host system. These registers are polled during power up initialization and contain specific device and add-in card product information including Vendor ID, Device ID, Revision and the amount of memory required for product operation. The S5935 can either load these registers with default values or initialize them from an external non-volatile memory area called `Configuration Space'. The S5935 can accommodate a total of 256 bytes of external memory for this purpose. The first 64 bytes is reserved for user defined configuration data which is loaded into the PCI Configuration Registers during power-up initialization. The remaining 192 bytes may be used to implement an Expansion BIOS or contain add-in card POST code. Table 1 shows all the S5935 PCI Configuration Registers. PCI Operation Registers The second group of registers are the PCI Operation Registers shown in Table 2. This group consists of sixteen 32-bit (DWORD) registers accessible to the Host processor from the PCI Local bus. These are the main registers through which the PCI Host configures S5935 operation and communicates with the Add-On Local bus. These registers encompass the PCI bus incoming and outgoing Mailboxes, FIFO data channel, Bus Master Address and Count registers, Pass-Thru data channel registers and S5935 device Status and Control registers. Table 1. PCI Configuration Registers
Byte 3 Byte 2 Byte 1 Byte 0 Address
00h 04h 08h 0Ch
Device ID PCI Status Class Code Built-in Self Test Header Type
Vendor ID PCI Command Revision ID Latency Timer Cache Line Size
Base Address Register 0 Base Address Register 1 Base Address Register 2 Base Address Register 3 Base Address Register 4 Reserved Reserved Space Reserved Space Expansion ROM Base Address Reserved Space Reserved Space Max. Latency Min. Grant Interrupt Pin Interrupt Line
10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch
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Add-On Bus Operation Registers The third and last register group consists of the AddOn Operation Registers, shown in Table 3. This group of eighteen 32-bit (DWORD) registers is accessible to the Add-On Local bus. These are the main registers through which the Add-On logic configures S5935 operation and communicates with the PCI Local bus. These registers encompass the Add-On bus Mailboxes, Add-On FIFO, DMA Address/Count Registers (when Add-On initiated Bus Mastering), Pass-Thru Registers and Status/Control registers. Table 2. PCI Operation Registers
PCI Operation Registers
Outgoing Mailbox Register 1 (OMB1) Outgoing Mailbox Register 2 (OMB2) Outgoing Mailbox Register 3 (OMB3) Outgoing Mailbox Register 4 (OMB4) Incoming Mailbox Register 1 (IMB1) Incoming Mailbox Register 2 (IMB2) Incoming Mailbox Register 3 (IMB3)
Table 2. PCI Operation Registers
PCI Operation Registers
Incoming Mailbox Register 4 (IMB4) FIFO Register Port (bidirectional) (FIFO) Master Write Address Register (MWAR) Master Write Transfer Count Register (MWTC) Master Read Address Register (MRAR) Master Read Transfer Count Register (MRTC) Mailbox Empty/Full Status Register (MBEF)
Address Offset
1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch
Address Offset
00h 04h 08h 0Ch 10h 14h 18h
Interrupt Control/Status Register (INTCSR) Bus Master Control/Status Register (MCSR)
Non-Volatile Memory Interface The S5935 contains a set of PCI Configuration Registers. These registers can be initialized with default values or with designer specified values contained in an external nvRAM. The nvRAM can be either a serial (2 Kbytes, maximum) or a byte-wide device (64 Kbytes, maximum).
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The optional nvRAM allows the Add-On card manufacturer to initialize the S5935 with his specific Vendor ID and Device ID numbers along with desired S5935 operation characteristics. The non-volatile memory feature also provides for the Expansion BIOS and POST code (power-on-self-test) options on the PCI bus. Table 3. Add-On Bus Operation Registers
Add-On Bus Operation Registers
Incoming Mailbox Register 1 (AIMB1) Incoming Mailbox Register 2 (AIMB2) Incoming Mailbox Register 3 (AIMB3) Incoming Mailbox Register 4 (AIMB4) Outgoing Mailbox Register 1 (AOMB1) Outgoing Mailbox Register 2 (AOMB2) Outgoing Mailbox Register 3 (AOMB3) Outgoing Mailbox Register 4 (AOMB4) FIFO Port (AFIFO) Bus Master Write Address Register (MWAR) Pass-Thru Address Register (APTA) Pass-Thru Data Register (APTD) Bus Master Read Address Register (MRAR) Mailbox Empty/Full Status Register (AMBEF) Interrupt Control/Status Register (AINT) General Control/Status Register (ARCR) Bus Master Write Transfer Count (MWTC) Bus Master Read Transfer Count (MRTC)
Mailbox Operation The Mailbox Registers are divided into two four DWORD sets. Each set is dedicated to one bus for transferring data to the other bus. Figure 3 below shows a block diagram of the mailbox section of the S5935. The provision of Mailbox Registers provides an easy path for the transfer of user information (command, status or parametric data) between the two buses. An empty/full indication for each Mailbox Register, at the byte level, is determined by polling a Status Register accessible to both the PCI and AddOn buses. Providing Mailbox byte level empty/full indications allows for greater flexibility in 8-, 16- or 32-bit system interfaces. i.e., transferring a single byte to an 8-bit Add-On bus without requiring the assembling or disassembling of 32-bit data. The generation of interrupts from Mailbox Registers is equivalent with the commonly known `DOORBELL' interrupt technique. Bit locations configured within the S5935's Operation Registers select a Mailbox and Mailbox byte which is to generate an interrupt when full or touched. A mailbox interrupt control register is then used to enable interrupt generation and to select if the interrupt is to be generated on the PCI or Add-On Local bus. PCI Local bus interrupts may also be generated from direct hardware interfacing due to a unique AMCC feature. A dedicated Mailbox byte is directly accessible via a set of hardware device signal pins. A mailbox load signal pin latches Add-On bus data directly into the Mailbox initiating a PCI bus interrupt if enabled. Mailbox data may also be read in a similar manner. This option is shared with the byte wide non-volatile memory signal pins. The S5935 must use the serial nvRAM for the direct mailbox option signal pins to be available or they are assigned to the byte wide at power up.
Address
00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 58h 5Ch
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Figure 3.
S5935
PCI MB1 Byte 0 PCI MB1 Byte 1 PCI MB1 Byte 2 PCI MB2 Byte 0 PCI MB2 Byte 1 PCI MB2 Byte 2 PCI MB2 Byte 3 Add MB2 Byte 0 Add MB2 Byte 1 Add MB2 Byte 2 Add MB2 Byte 3 PCI MB3 Byte 0 PCI MB3 Byte 1 PCI MB3 Byte 2 PCI MB3 Byte 3 Add MB3 Byte 0 Add MB3 Byte 1 Add MB3 Byte 2 Add MB3 Byte 3 PCI MB4 Byte 0 PCI MB4 Byte 1
PCI MB1 Byte 3 Add MB1 Byte 0 Add MB1 Byte 1 Add MB1 Byte 2 Add MB1 Byte 3
PCI MB4 Byte 3 Add MB4 Byte 0 Add MB4 Byte 1 Add MB4 Byte 2 Add MB4 Byte 3
Mailbox Status Register
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PCI MB4 Byte 2
PCI Local Bus
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Pass-Thru Operation Pass-Thru operation executes PCI bus cycles in real time with the Add-On bus. This allows the PCI bus to directly read or write to Add-On resources. The S5935 allows the designer to declare up to four individual Pass-Thru Regions. Each region may be defined as 8, 16-, or 32-bits wide, mapped into host memory or I/O space and may be up to 512MB bytes in size. Figure 4 right shows a block diagram of the S5935 Pass-Thru architecture. Pass-Thru operations are performed in PCI target only mode, making this data channel useful for converting existing ISA or EISA designs over to the fast PCI architecture. The Pass-Thru data channel utilizes separate Add-On bus signal pins to reflect a PCI bus read or write request. Add-On logic decodes these signals to determine if it must read or write data to the S5935 to satisfy the request. Information decoded includes PCI request occurring, the byte lanes involved, the specific Pass-Thru region accessed and if the request is a burst or single-cycle access. All requested PassThru address and data information is passed via AddOn Operation Registers. Pass-Thru operation supports single PCI data cycles and PCI data bursts. During PCI burst operations, the S5935 is capable of transferring data at the full PCI bandwidth. Should slower Add-On logic be implemented, the S5935 automatically issues PCI bus waits or a Host retry indication until the requested transfer is satisfied. Figure 4.
S5935
Address Latch
PCI Local Bus
FIFO PCI Bus Mastering Operation FIFO PCI Bus Master data transfers are processed by one of two 8-DWORD FIFOs. The FIFO block diagram is shown in Figure 5. The particular FIFO selected for a data transfer is dependent only on the direction of data flow and is completely transparent to the user. Internal S5935 decode logic selects the FIFO that is dedicated to transferring data to the other bus. The way data is transferred by a FIFO, is determined by Operation and Configuration Registers contained within the S5935. A FIFO may be configured for either PCI or Add-On initiated Bus Mastering with programmable byte advance conditions, read vs. write priorities and Add-On bus widths. Advance conditions allow the FIFO to implement 8-, 16- or 32-bit bus widths. Configuring the S5935 for Bus Master operation enables separate address and data count registers, which are loaded with the PCI memory address location and number of bytes to be read or written. This is accomplished by either the Host CPU or Add-On logic. Data can be transferred between the two buses transparent to the PCI Host processor, however, the Add-On logic is required to service the S5935 Add-On Local bus. An indication of transfer completion can be seen by polling a status register done bit or S5935 signal pin or enabling a `transfer count = 0' interrupt to either bus. Further FIFO configuration bits select 16, 32, or 64 bit Endian conversion options for incoming and outgoing data. Endian conversion allows an Add-On processor and the host to transfer data in their native Endian format. Other configuration bits determine if the Add-On Local bus width is 8, 16 or 32 bits. 16-bit bus configurations internally steer FIFO data from the upper 16 bits of the DWORD and then to the lower 16-bits on alternate accesses. FIFO pointers are then updated when appropriate bytes are accessed. Other methods are available for 8-bit or 16-bit Add-Ons. Efficient FIFO management configuration schemes unique to the AMCC S5935 specify how full or empty a FIFO must be before it requests the PCI Local bus. These criteria include bus requests when any of the 8 DWORDs are empty, or when four or more DWORDs are empty. This allows the designer to control how often the S5935 requests the bus. The S5935 always attempts to perform burst operations to empty or fill the FIFOs. Further FIFO capabilities over the standard register access methods allow for direct hardware FIFO access. This is provided through separate access pins on the S5935. Other status output pins allow for easily cascading external FIFOs to the AddOn design.
Add-On Pass-Thru W Data rite
Add-On Pass-Thru Read Data
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Add-On PassThru Address Register
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Figure 5.
S5935
B0 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3
Endian Converter
B1 B2 B3
PCI Local Bus
B0 B1 B2 B3
B0 B1 B2 B3
B0 B1 B2 B3
B0 B1 B2 B3
B0 B1 B2 B3
B0 B1 B2 B3
B0 B1 B2 B3
B0 B1 B2 B3
Endian Converter
32-Bit Master Write Address Register 32-Bit Master ReadAddress Register 30-Bit Master Read Count Register 28-Bit Master Write Count Register
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Figure 6. S5933 Pin Assignment
DQ0 100 DQ1 99 DQ2 98 96 95 94 92 88 86 84 83 82 80 79 78 76 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
56 AD0 55 AD1 54 AD2 52 AD3 48 AD4 47 AD5 46 AD6 44 AD7 42 AD8 40 AD9 39 AD10 38 AD11 36 AD12 35 AD13 34 AD14 32 AD15 14 AD16 12 AD17 8 AD18 7 AD19 6 AD20 4 AD21 3 AD22 2 AD23 158 AD24 156 AD25 155 AD26 154 AD27
S5935 Matchmaker
DQ16 157 DQ17 145 DQ18 133 DQ19 125 DQ20 117 DQ21 105 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BPCLK 93 85 77 65 53 45 37 25 13 5 140
ADD-ON Local Bus
PCI Local Bus
152 AD28 148 AD29 147 AD30 146 AD31 43 C/BE0# 28 C/BE1# 15 C/BE2# 159 C/BE3# 144 REQ# 143 GNT# 16 FRAME# 20 DEVSEL# 18 IRDY# 19 TRDY# 160 IDSEL 22 STOP# 23 LOCK# 27 PAR 24 PERR# 26 SERR# 142 CLK 139 RST# 58 INTA#
IRQ# 124 SYSRST# 126 ADR2 ADR3 ADR4 ADR5 ADR6 BE0# BE1# BE#2 BE3#/ADR1 SELECT# WR# RD# 68 67 66 64 132 87 63 62 60 75 74 72
ADD-ON Local Bus Controls
ADD-ON Local Bus Register Controls
PTNUM0 123 PTNUM1 122 PTBE0# PTBE1# PTBE2# PTBE3# 116 118 119 120
Pass-Thru Data Controls
Device Controls
MODE 138 RSVD 135 SNV
59
PTATN# 114 PTBURST# 112 PTADR# PTWR PTRDY# WRFULL WRFIFO# 107 108 115 103 102
10 30 50 70
Vss Vss Vss Vss
RDEMPTY 106 RDFIFO# 104 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 FWE/EA14 57 61 69 73 81 89 97 101 109 113 121 129 137 141 149
FIFO Data Controls
90 Vss 110 Vss 130 Vss 150 Vss
Power & Ground
11 31 51 71
Vdd Vdd Vdd Vdd
91 Vdd 111 Vdd 131 Vdd 151 Vdd
Byte Wide NVRAM Data
FRF/EA15 153 EQ0 EQ1 EQ2 EQ3 FWC#/EQ4 FRC#/EQ5 AMREN/EQ6 AMWEN/EQ7 EWR#/SDA ERD#/SCL 1 9 17 21 29 33 41 49 127 128 NVRAM Data Bus
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Signal Type Definition The following signal type definitions [in, out, t/s, s/t/s and o/d] are taken from Revision 2.1 of the PCI local bus specification.
Input is a standard input-only signal. Totem Pole Output is a standard active driver. Tri-State (R) is a bidirectional, tristate input/output pin. Sustained Tri-State is an active low tristate signal owned and driven by one and only one agent at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central source. Open Drain allows multiple devices to share as a wire-OR.
in out t/s
s/t/s o/d
Note that a # symbol at the end of a signal name denotes that the active state occurs when the signal is at a low voltage. When no # symbol is present, the signal is active high.
Figure 7. S5935 Signal Pins
S5935
PCLK INTA# RST# BPCLK IRQ# SYSRST
Add-On Bus Control Add-On Data Bus
AD[31:0]
DQ[31:0]
C/BE[3:0]#
SELECT# ADR[6:2]
PCI 2.1 Local Bus
REQ# GNT# FRAME# DEVSEL# IRDY# TRDY# IDSEL
BE[3:0]# RD# WR#
S5933 Register Access
PTATN# PTBURST# PTNUM[1:0] PTBE[3:0]#
STOP# LOCK#
PTADR# PTWR PTRDY#
Pass-Thru Control/ Access
PAR# PERR# SERR# RDFIFO# WRFIFO# RDEMPTY WRFULL
Direct FIFO Access Byte Wide Config/BIOS Opt. Serial Config/BIOS Opt.
EA[15:0] EQ[7:0]
S5935 Control
MODE RSVD SNV EWR#/SDA ERD#/SCL
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Address and Data Pins -- PCI Local Bus
Signal AD[31:00] Type t/s Description Local Bus Address/Data lines. Address and data are multiplexed on the same pins. Each bus operation consists of an address phase followed by one or more data phases. Address phases are identified when the control signal, FRAME#, is asserted. Data transfers occur during those clock cycles in which control signals IRDY# and TRDY# are both asserted. Bus Command and Byte Enables. These are multiplexed on the same pins. During the address phase of a bus operation, these pins identify the bus command, as shown in the table below. During the data phase of a bus operation, these pins are used as Byte Enables, with C/BE[0]# enabling byte 0 (least significant byte) and C/BE[3]# enabling byte 3 (most significant byte). C/BE[3:0]# 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PAR t/s 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description (during address phase) Interrupt Acknowledge Special Cycle I/O READ I/O WRITE Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write MEMORY READ - Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
C/BE[3:0]#
t/s
Parity. This signal is even parity across the entire AD[31:00] field along with the C/BE[3:0]# field. The parity is stable in the clock following the address phase and is sourced by the master. During the data phase for write operations, the bus master sources this signal on the clock following IRDY# active; during the data phase for read operations, this signal is sourced by the target and is valid on the clock following TRDY# active. The PAR signal therefore has the same timing as AD[31:00}, delayed by one clock.
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System Pins -- PCI Local Bus
Signal CLK Type in Description Clock. The rising edge of this signal is the reference upon which all other signals are based, with the exception of RST# and the interrupt (IRQA#-). The maximum frequency for this signal is 33 MHz and the minimum is DC (0 Hz). Reset. This signal is used to bring all other signals within this device to a known, consistent state. All PCI bus interface output signals are not driven (tri-stated), and open drain signals such as SERR# are floated.
RST#
in
Interface Control Pins -- PCI Bus Signal
Signal FRAME# Type s/t/s Description Frame. This signal is driven by the current bus master and identifies both the beginning and duration of a bus operation. When FRAME# is first asserted, it indicates that a bus transaction is beginning and that valid addresses and a corresponding bus command are present on the AD[31:00] and C/BE[3:0] lines. FRAME# remains asserted during the data transfer portion of a bus operation and is deasserted to signify the final data phase. Initiator Ready. This signal is sourced by the bus master and indicates that the bus master is able to complete the current data phase of a bus transaction. For write operations, it indicates that valid data is on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted together. Target Ready. This signal is sourced by the selected target and indicates that the target is able to complete the current data phase of a bus transaction. For read operations, it indicates that the target is providing valid data on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted together. Stop. The Stop signal is sourced by the selected target and conveys a request to the bus master to stop the current transaction. Lock. The lock signal provides for the exclusive use of a resource. The S5935 may be locked as a target by one master at a time. The S5935 cannot lock a target when it is a master. Initialization Device Select. This pin is used as a chip select during configuration read or write operations. Device Select. This signal is sourced by an active target upon decoding that its address and bus commands are valid. For bus masters, it indicates whether any device has decoded the current bus cycle.
IRDY#
s/t/s
TRDY#
s/t/s
STOP# LOCK# IDSEL DEVSEL#
s/t/s in in s/t/s
Arbitration Pins (Bus Masters Only) -- PCI Local Bus
Signal REQ# GNT# Type out in Description Request. This signal is sourced by an agent wishing to become the bus master. It is a point-to-point signal and each master has its own REQ#. Grant. The GNT# signal is a dedicated, point-to-point signal provided to each potential bus master and signifies that access to the bus has been granted.
Error Reporting Pins -- PCI Local Bus
Signal PERR# Type s/t/s Description Parity Error. This pin is used for reporting parity errors during the data portion of a bus transaction for all cycles except a Special Cycle. It is sourced by the agent receiving data and driven active two clocks following the detection of the error. This signal is driven inactive (high) for one clock cycle prior to returning to the tri-state condition.
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Error Reporting Pins -- PCI Local Bus
Signal SERR# Type o/d Description System Error. This pin is used for reporting address parity errors, data parity errors on Special Cycle commands, or any error condition having a catastrophic system impact.
Interrupt Pin -- PCI Local Bus
Signal INTA# Type o/d Description Interrupt A. This pin is a level sensitive, low active interrupt to the host. The INTA# interrupt must be used for any single function device requiring an interrupt capability.
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NON-VOLATILE MEMORY INTERFACE SIGNALS
This signal grouping provides for connection to external non-volatile memories. Either a serial or byte-wide device may be used. The serial interface shares the read and write control pins used for interfacing with byte-wide memory devices. Since it is intended that only one (serial or byte wide) configuration be used in any given implementation, separate descriptions are provided for Serial nv Devices
Signal SCL Type t/s Description Serial Clock. This output is intended to drive a two-wire Serial Interface and functions as the bus's master. It is intended that this signal be directly connected to one or more inexpensive serial non-volatile RAMs or EEPROMs. This pin is shared with the byte wide interface signal, ERD#. Serial Data/Address. This bidirectional pin is used to transfer addresses and data to or from a serial nvRAM or EEPROM. It is an open drain output and intended to be wire-ORed with all other devices on the serial bus using a 4.7K external pull-up resistor. This pin is shared with the byte wide interface signal, EWR#. Serial Non-Volatile Device. This input, when high, indicates a serial boot device or no boot device is present. When this pin is low, a byte-wide boot device is present.
each. The S5935 provides the pins necessary to interface to a byte wide non-volatile memory. When they are connected to a properly configured serial memory, these byte wide interface pins assume alternate functions. These alternate functions include added external FIFO status flags, FIFO reset control, Add-On control for bus mastering and a hardware interface mailbox port.
SDA
t/s
SNV
in
Note: SCL and SDA are not controlled by FLT#.
Byte-Wide nv Devices
Signal EA[15:00] Type t/s Description External nv memory address. These signals connect directly to the external BIOS (or EEPROM) or EPROM address pins EA0 through EA15. The PCI interface controller assembles 32-bit-wide accesses through multiple read cycles of the 8-bit device. The address space from 0040h through 007Fh is used to preload and initialize the PCI configuration registers. Should an external nv memory be used, the minimum size required is 128 bytes and the maximum is 64K bytes. When a serial memory is connected to the S5935, the pins EA[7:0] are reconfigured to become a hardware Add-On to PCI mailbox register with the EA8 pin as the mailbox load clock. Also, the EA15 signal pin will provide an indication that the PCI to Add-On FIFO is full (FRF#), and the EA14 signal pin will indicate whether the Add-On to PCI FIFO is empty (FWE#). External nv memory read control. This pin is asserted during read operations involving the external non-volatile memory. Data is transferred into the S5935 during the low to high transition of ERD#. This pin is shared with the serial external memory interface signal, SCL. External nv memory write control. This pin is asserted during write operations involving the external non-volatile memory. Data is presented on pins EQ[7:0] along with its address on pins EA[15:0] throughout the entire assertion of EWR#. This pin is shared with the serial external memory interface signal, SDA. External memory data bus. These pins are used to directly connect with the data pins of an external non-volatile memory. When a serial memory is connected to the S5935, the pins EQ4, EQ5, EQ6 and EQ7 become reconfigured to provide signal pins for bus mastering control from the Add-On interface.
ERD#
out
EWR#
t/s
EQ[7:0]
t/s
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ADD-ON BUS INTERFACE SIGNALS
The following sets of signals represent the interface pins available for the Add-On function. There are four Register Access Pins
Signal DQ[31:00] Type t/s Description Datapath DQ0-DQ31. These pins represent the datapath for the Add-On peripheral's data bus. They provide the interface to the controller's FIFO and other registers. When MODE=V CC, only DQ[15:00] are used. DQ[31:0] have internal pull-up resistors. Add-On Addresses. These signals are the address lines to select which of the 16 DWORD registers within the controller is desired for a given read or write cycle, as shown in the table below. ADR[6:2] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 BE3# or ADR1 in 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Register Name Add-On Incoming Mailbox Reg. 1 Add-On Incoming Mailbox Reg. 2 Add-On Incoming Mailbox Reg. 3 Add-On Incoming Mailbox Reg. 4 Add-On Outgoing Mailbox Reg. 1 Add-On Outgoing Mailbox Reg. 2 Add-On Outgoing Mailbox Reg. 3 Add-On Outgoing Mailbox Reg. 4 Add-On FIFO Port Bus Master Write Address Register Add-On Pass-Thru Address Add-On Pass-Thru Data Bus Master Read Address Register Add-On Mailbox Empty/Full Status Add-On Interrupt Control Add-On General Control/Status Register Bus Master Write Transfer Count Bus Master Read Transfer Count
groups: Register access, FIFO access, Pass-Thru mode pins, and general system pins.
ADR[6:2]
in
Byte Enable 3 (32-bit mode) or ADR1 (16 bit mode). This pin is used in conjunction with the read or write strobes (RD# or WR#) and the Add-On select signal, SELECT#. As a Byte Enable, it is necessary to have this pin asserted to perform write operations to the register identified by ADR[6:2] bit locations d24 through d31; for read operations it controls the DQ[31:24] output drive. Byte Enable 2 through 0. These pins provide for individual byte control during register read or write operations. BE2# controls activity over DQ[23:DQ16], BE1# controls DQ[15:8], and BE0# controls DQ[7:0]. During read operations they control the output drive for each of their respective byte lanes; for write operations they serve as a required enable to perform the modification of each byte lane.
BE[2:0]#
in
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Register Access Pins (Continued)
Signal SELECT# Type in Description Select for the Add-On interface. This signal must be driven low for any write or read access to the AddOn interface registers. This signal must be stable during the assertion of command signals WR# or RD#. Write strobe. This pin, when asserted in conjunction with the SELECT# pin, causes the writing of one of the internal registers. The specific register and operand size are identified through address pins ADR[6:2] and the byte enables, BE[3:0]#. Read strobe. This pin, when asserted in conjunction with the SELECT# pin, causes the reading of one of the internal registers. The specific register and operand size are identified through address pins ADR[6:2] and the byte enables BE[3:0]#. This pin control whether the S5935 data accesses on the DQ bus are to be 32-bits wide (MODE = low) or 16-bits wide (MODE = high). When in the 16 bit mode, the signal BE3# is reassigned as the address signal ADR1.
WR#
in
RD#
in
MODE
in
FIFO Access Pins
Signal WRFIFO# Type in Description Write FIFO. This signal provides a method to directly write the FIFO without having to generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO. Access width is either 32 bits or 16 bits depending on the data bus size available. This signal is intended for implementing PCI DMA transfers with the Add-On system. Read FIFO. This signal provides a method to directly read the FIFO without having to generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO. Access width is either 32 bits or 16 bits, depending on the data bus size defined by the MODE pin. This signal is intended for implementing PCI DMA transfers with the Add-On system. WRFULL out Write FIFO full. This pin indicates whether the Add-On-to-PCI bus FIFO is able to accept more data. This pin is intended to be used to implement DMA hardware on the Add-On system bus. A logic low output from this pin can be used to represent a DMA write (Add-On to-PCI FIFO) request. Read FIFO Empty. This pin indicates whether the read FIFO (PCI-to-Add-On FIFO) contains data. This pin is intended to be used by the Add-On system to control DMA transfers from the PCI bus to the Add-On system bus. A logic low from this pin can be used to represent a DMA (PCI-to-Add-On FIFO) request.
RDFIFO#
in
RDEMPTY
out
Pass-Thru Interface Pins
Signal PTATN# PTBURST# PTRDY# PTNUM[1:0] Type out out in out Description Pass-Thru Attention. This signal identifies that an active PCI bus cycle has been decoded and data must be read from or written to the Pass-Thru Data Register. Pass-Thru Burst. This signal identifies PCI bus operations involving the current Pass-Thru cycle as requesting burst access. Pass-Thru Ready. This input indicates when Add-On logic has completed a Pass-Thru cycle and another may be initiated. Pass-Thru Number. These signals identify which of the four base address registers decoded a PassThru bus activity. These bits are only meaningful when signal PTATN# is active. A value of 00 corresponds to Base Address Register 1, a value of 01 for Base Address Register 2, and so on. Pass-Thru Byte Enables. These signals indicate which bytes are requested for a given Pass-Thru operation. They are valid during the presence of signal PTATN# active.
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Pass-Thru Interface Pins
Signal PTADR# Type in Description Pass-Thru Address. This signal causes the actual Pass-Thru requested address to be presented as outputs on the DQ pins DQ[31:0] for Add-Ons with 32-bit buses, or the low-order 16 bits for Add-Ons with 16-bit buses. It is necessary that all other bus control signals be in their inactive state during the assertion of PTADR#. The purpose of this signal is to provide the direct addressing of external AddOn peripherals through use of the PTNUM[1:0] and the low-order address bits presented on the DQ bus with this pin active. Pass-Thru Write. This signal identifies whether a Pass-Thru operation is a read or write cycle. This signal is valid only when PTATN# is active.
PTWR
out
System Pins
Signal SYSRST# Type out Description System Reset. This low active output is a buffered form of the PCI bus reset, RST#. It is not synchronized to any clock within the PCI interface controller. Additionally, this signal can be invoked through software from the PCI host interface. Buffered PCI Clock. This output is a buffered form of the PCI bus clock and, as such, has all of the behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability). Interrupt. This pin is used to signal the Add-On system that a significant event has occurred as a result of activity within the PCI controller. Reserved. This pin must be left open at all times.
BPCLK IRQ# RSVD
out out in
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PCI CONFIGURATION REGISTERS
Each PCI bus device contains a unique 256-byte region called its configuration header space. Portions of this configuration header are mandatory in order for a PCI agent to be in full compliance with the PCI specTable 4. Configuration Registers
Configuration Address Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 10h-27h 28h-2Fh 30h 34h-3Bh 3Ch 3Dh 3Eh 3Fh 40h-FFh VID DID PCICMD PCISTS RID CLCD CALN LAT HDR BIST BADR0-BADR5 -- EXROM -- INTLN INTPIN MINGNT MAXLAT -- Abbreviation Register Name Vendor Identification Device Identification PCI Command Register PCI Status Register Revision Identification Register Class Code Register Cache Line Size Register Master Latency Timer Header Type Built-in Self-test Base Address Registers (0-5) Reserved Expansion ROM Base Address Reserved Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Not used
ification. This section describes each of the configuration space fields--its address, default values, initialization options, and bit definitions--and also provides an explanation of its intended usage.
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PCI Configuration Space Header
31 24 23 DEVICE ID STATUS
BIST
16 15
87 VENDOR ID COMMAND REV ID LATENCY TIMER CACHE LINE SIZE
00 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C
CLASS CODE HEADER TYPE = 0
BASE ADDRESS REGISTER #0 BASE ADDRESS REGISTER #1 BASE ADDRESS REGISTER #2 BASE ADDRESS REGISTER #3 BASE ADDRESS REGISTER #4 BASE ADDRESS REGISTER #5 RESERVED = 0's RESERVED = 0's EXPANSION ROM BASE ADDRESS RESERVED = 0's RESERVED = 0's MIN_GNT INTERRUPT PIN
MAX_LAT
INTERRUPT LINE
LEGEND
EPROM IS DATA SOURCE (READ ONLY) CONTROL FUNCTION EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT) EPROM INITIALIZED RAM (CAN BE ALTERED FROM ADD-ON PORT) HARD-WIRED TO ZEROES Note: Some registers are a combination of the above. See individual sections for full description.
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VENDOR IDENTIFICATION REGISTER (VID)
Register Name Address Offset Power-up value Boot-load Attribute Size Vendor Identification 00h-01h 10E8h (AMCC, Applied Micro Circuits Corp.) External nvRAM offset 040h-41h Read Only (RO) 16 bits
The VID register contains the vendor identification number. This number is assigned by the PCI Special Interest Group and is intended to uniquely identify any PCI device. Write operations from the PCI interface have no effect on this register. After reset is removed, this field can be boot-loaded from the external non-volatile device (if present and valid) so that other legitimate PCI SIG members can substitute their vendor identification number for this field.
Figure 8. Vendor Identification Register
15 10E8h
0
Vendor Identification Register (RO)
Table 5. Vendor Identification Register
Bit 15:0 Description
Vendor Identification Number: This is a 16 bit-value assigned to AMCC.
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DEVICE IDENTIFICATION REGISTER (DID)
Register Name Address Offset Power-up value Boot-load Attribute Size Device Identification 02h-03h 4750h (ASCII hex for `GP', General Purpose) External nvRAM offset 042h-43h Read Only 16 bits
The DID register contains the vendor-assigned device identification number. This number is generated by AMCC in compliance with the conditions of the PCI specification. Write operations from the PCI interface have no effect on this register. After reset is removed, this field can be boot-loaded from the external non-volatile device (if present and valid) so that other legitimate PCI SIG members can substitute their own device identification number for this field.
Figure 9. Device Identification Register
15 4750h
0
Device Identification Register (RO)
Table 6. Device Identification Register
Bit 15:0 Description Device Identification Number: This is a 16-bit value initially assigned by AMCC for applications using the AMCC Vendor ID.
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PCI COMMAND REGISTER (PCICMD)
Register Name Address Offset Power-up value Boot-load Attribute Size PCI Command 04h-05h 0000h not used Read/Write (R/W on 6 bits, Read Only for all others) 16 bits
This 16-bit register contains the PCI Command. The function of this register is defined by the PCI specification and its implementation is required of all PCI devices. Only six of the ten fields are used by this device; those which are not used are hardwired to 0. The definitions for all fields are provided here for completeness.
Figure 10. PCI Command Register
15 Reserved = 00's
9 0X
8 X0
7
6
5 0
4 0
3 0
2 X
1 X
0 X
Fast Back-to-Back SERRE Wait Cycle Enable Parity Error Enable Palette Snoop Enable Memory Write and Invalidate Enable Special Cycle Enable Bus Master Enable Memory Access Enable I/O Access Enable
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Table 7. PCI Command Register
Bit 15:10 9 8 Reserved. Equals all 0's. Fast Back-to-Back Enable. The S5935 does not support this function. This bit must be set to zero. This bit is cleared to a 0 upon RESET#. System Error Enable. When this bit is set to 1, it permits the S5935 controller to drive the open drain output pin, SERR#. This bit is cleared to 0 upon RESET#. The SERR# pin driven active normally signifies a parity error on the address/control bus. Wait Cycle Enable. This bit controls whether this device does address/data stepping. Since the S5935 controller never uses stepping, it is hardwired to 0. Parity Error Enable. This bit, when set to a one, allows this controller to check for parity errors. When a parity error is detected, the PCI bus signal PERR# is asserted. This bit is cleared (parity testing disabled) upon the assertion of RESET#. Palette Snoop Enable. This bit is not supported by the S5935 controller and is hardwired to 0. This feature is used solely for PCI-based VGA devices. Memory Write and Invalidate Enable. This bit allows certain Bus Master devices to use the Memory Write and Invalidate PCI bus command when set to 1. When set to 0, masters must use the Memory Write command instead. The S5935 controller does not support this command when operated as a master and therefore it is hardwired to 0. Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when this bit is set to 1. The S5935 controller does not monitor (or generate) special cycles and this bit is hardwired to 0. Bus Master Enable. This bit, when set to a one, allows the S5935 controller to function as a bus master. This bit is initialized to 0 upon the assertion of signal pin RESET#. Memory Space Enable. This bit allows the S5935 controller to decode and respond as a target for memory regions that may be defined in one of the five base address registers. This bit is initialized to 0 upon the assertion of signal pin RESET#. Space Enable. This bit allows the S5935 controller to decode and respond as a target to I/O cycles which are to regions defined by any one of the five base address registers. This bit is initialized to 0 upon the assertion of signal pin RESET#. Description
7 6
5 4
3 2 1
0 I/O
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PCI STATUS REGISTER (PCISTS)
Register Name Address Offset Power-up value Boot-load Attribute Size PCI Status 06h-07h 0080h not used Read Only (RO), Read/Write Clear (R/WC) 16 bits
This 16-bit register contains the PCI status information. The function of this register is defined by the PCI specification and its implementation is required of all PCI devices. Only some of the bits are used by this device; those which are not used are hardwired to 0. Most status bits within this register are designated as "write clear," meaning that in order to clear a given bit, the bit must be written as a 1. All bits written with a 0 are left unchanged. These bits are identified in Figure 4 as (R/WC). Those which are Read Only are shown as (RO) in Figure 4.
Figure 11. PCI Status Register
15 X 14 X 13 X 12 X 11 X 10 0 9 0 8 X 70 6 0 Reserved (RO) = 00's Reserved (RO) Fast Back-to-Back (RO) Data Parity Reported (R/WC) DEVSEL# Timing Status (RO) 0 0 = Fast (S5933) 0 1 = Medium 1 0 = Slow 1 1 = Reserved Signaled Target Abort (R/WC) Received Target Abort (R/WC) Received Master Abort (R/WC) Signaled System Error (R/WC) Detected Parity Error (R/WC)
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Table 8. PCI Status Register
Bit 15 14 13 12 11 10:9 8 Description Detected Parity Error. This bit is set whenever a parity error is detected. It functions independently from the state of Command Register Bit 6. This bit may be cleared by writing a 1 to this location. Signaled System Error. This bit is set whenever the device asserts the signal SERR#. This bit can be reset by writing a 1 to this location. Received Master Abort. This bit is set whenever a bus master abort occurs. This bit can be reset by writing a 1 to this location. Received Target Abort. This bit is set whenever this device has one of its own initiated cycles terminated by the currently addressed target. This bit can be reset by writing a 1 to this location. Signaled Target Abort. This bit is set whenever this device aborts a cycle when addressed as a target. This bit can be reset by writing a 1 to this location. Device Select Timing. These bits are read-only and define the signal behavior of DEVSEL# from this device when accessed as a target. Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involving the S5935 device as the master. The Parity Error Enable bit (D6 of the Command Register) must be set in order for this bit to be set. Once set, it can only be cleared by either writing a 1 to this location or by the assertion of the signal RESET#. Fast Back-to-back Capable. When equal to 1, this indicates that the device can accept fast back-to-back cycles as a target. Reserved. Equal all 0's.
7 6:0
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REVISION IDENTIFICATION REGISTER (RID)
Register Name Address Offset Power-up value Boot-load Attribute Size Revision Identification 08h 00h External nvRAM/EPROM offset 048h Read Only 8 bits
The RID register contains the revision identification number. This field is initially cleared. Write operations from the PCI interface have no effect on this register. After reset is removed, this field can be boot-loaded from the external non-volatile device (if present and valid) so that another value may be used.
Figure 12. Revision Identification Register
7 00h
0
Revision Identification Number (RO)
Table 9. Revision Identification Register
Bit 7:0 Description Revision Identification Number. Initialized to zeros, this register may be loaded to the value in non-volatile memory at offset 048h.
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CLASS CODE REGISTER (CLCD)
Register Name Address Offset Power-up value Boot-load Attribute Size Class Code 09h-0Bh FF0000h External nvRAM offset 049h-4Bh Read Only 24 bits
This 24-bit, read-only register is divided into three onebyte fields: the base class resides at location 0Bh, the sub-class at 0Ah, and the programming interface at 09h. The default setting for the base class is all ones (FFh), which indicates that the device does not fit into the thirteen base classes defined in the PCI Local Bus Specification. It is possible, however, through use of the external non-volatile memory, to implement one of the defined class codes described in Table 7 below. For devices that fall within the seven defined class codes, sub-classes are also assigned. Tables 8 through 20 describe each of the sub-class codes for base codes 00h through 0Ch, respectively.
Figure 13.
@0Bh 7 Base Class 0 7 Sub-Class @0Ah 0 7 Prog I/F @09h (Offset) 0 (Bit)
Table 10. Defined Base Class Codes
Base-Class 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0D-FEh FFh Early, pre-2.0 PCI specification devices Mass storage controller Network controller Display controller Multimedia device Memory controller Bridge device Simple communication controller Base system peripherals Input devices Docking stations Processors Serial bus controllers Reserved Device does not fit defined class codes (default) Description
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Table 11. Base Class Code 00h: Early, Pre-2.0 Specification Devices
Sub-Class 00h 01h Prog I/F 00h 00h Description All devices other than VGA VGA-compatible device
Table 12. Base Class Code 01h: Mass Storage Controllers
Sub-Class 00h 01h 02h 03h 04h 80h Prog I/F 00h xxh 00h 00h 00h 00h Description SCSI controller IDE controller Floppy disk controller IPI controller RAID controller Other mass storage controller
Table 13. Base Class Code 02h: Network Controllers
Sub-Class 00h 01h 02h 03h 80h Prog I/F 00h 00h 00h 00h 00h Ethernet controller Token ring controller FDDI controller ATM controller Other network controller Description
Table 14. Base Class Code 03h: Display Controllers
Sub-Class 00h 00h 01h 80h Prog I/F 00h 01h 00h 00h VGA-compatible controller 8514 compatible controller XGA controller Other display controller Description
Table 15. Base Class Code 04h: Multimedia Devices
Sub-Class 00h 01h 80h Prog I/F 00h 00h 00h Video device Audio device Other multimedia device Description
Table 16. Base Class Code 05h: Memory Controllers
Sub-Class 00h 01h 80h Prog I/F 00h 00h 00h RAM memory controller Flash memory controller Other memory controller Description
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Table 17. Base Class Code 06h: Bridge Devices
Sub-Class 00h 01h 02h 03h 04h 05h 06h 07h 80h Prog I/F 00h 00h 00h 00h 00h 00h 00h 00h 00h Host/PCI bridge PCI/ISA bridge PCI/EISA bridge PCI/Micro Channel bridge PCI/PCI bridge PCI/PCMCIA bridge NuBus bridge CardBus bridge Other bridge type Description
Table 18. Base Class Code 07h: Simple Communications Controllers
Sub-Class 00h Prog I/F 00h 01h 02h 00h 01h 02h 00h Description Generic XT compatible serial controller 16450 compatible serial controller 16550 compatible serial controller Parallel port Bidirectional parallel port ECP 1.X compliant parallel port Other communications device
01h
80h
Table 19. Base Class Code 08h: Base System Peripherals
Sub-Class 00h Prog I/F 00h 01h 02h 00h 01h 02h 00h 01h 02h 00h 01h 00h Generic 8259 PIC ISA PIC EISA PIC Generic 8237 DMA controller ISA DMA controller EISA DMA controller Generic 8254 system timer ISA system timer EISA system timers (2 timers) Generic RTC controller ISA RTC controller Other system peripheral Description
01h
02h
03h 80h
Table 20. Base Class Code 09h: Input Devices
Sub-Class 00h 01h 02h 80h Prog I/F 00h 00h 00h 00h Keyboard controller Digitizer (Pen) Mouse controller Other input controller Description
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Table 21. Base Class Code 0Ah: Docking Stations
Sub-Class 00h 80h Prog I/F 00h 00h Description Generic docking station Other type of docking station
Table 22. Base Class Code 0Bh: Processors
Sub-Class 00h 01h 02h 10h 40h Prog I/F 00h 00h 00h 00h 00h Intel386TM Intel486TM PentiumTM AlphaTM Co-processor Description
Table 23. Base Class Code 0Ch: Serial Bus Controllers
Sub-Class 00 01h 02h Prog I/F 00h 00h 00h FireWireTM (IEEE 1394) ACCESS.bus SSA Description
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CACHE LINE SIZE REGISTER (CALN)
Register Name Address Offset Power-up value Boot-load Attribute Size Cache Line Size 0Ch 00h, hardwired not used Read Only 8 bits
This register is hardwired to 0. The cache line configuration register is used by the system to define the cache line size in doubleword (64-bit) increments. This controller does not use the "Memory Write and Invalidate" PCI bus cycle commands when operating in the bus master mode, and therefore does not internally require this register. When operating in the target mode, this controller does not have the connections necessary to "snoop" the PCI bus and accordingly cannot employ this register in the detection of burst transfers that cross a line boundary.
Figure 14. Cache Line Size Register
7 00h Cache Line Size (RO) 0
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LATENCY TIMER REGISTER (LAT)
Register Name Address Offset Power-up value Boot-load Attribute Size Latency Timer 0Dh 00h External nvRAM offset 04Dh Read/Write, bits 7:3; Read Only bits 2:0 8 bits
The latency timer register has meaning only when this controller is used as a bus master and pertains to the number of PCI bus clocks that this master will be guaranteed. The nonzero value for this register is internally decremented after this device has been granted the bus and has begun to assert FRAME#. Prior to this latency timer count reaching zero, this device can ignore the removal of the bus grant and may continue the use of the bus for data transfers.
Figure 15. Latency Timer Register
7 X
6 X
5 X
4 X
3 X
2 0
1 0
0 0
Bit Value
Latency Timer value (R/W) # of clocks x 8
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HEADER TYPE REGISTER (HDR)
Register Name Address Offset Power-up value Boot-load Attribute Size Header Type 0Eh 00h External nvRAM offset 04Eh Read Only 8 bits
This register consists of two fields: Bits 6:0 define the format for bytes 10h through 3Fh of the device configuration header, and bit 7 establishes whether this device represents a single function (bit 7 = 0) or a multifunction (bit 7 = 1) PCI bus agent. The S5935 is a single function PCI device.
Figure 16. Header Type Register
7 X 6 5 4 00h Format field (Read Only) 3 2 1 0 Bit Value
Single/Multi-function device (Read Only) 0 = single function 1 = multi-function
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BUILT-IN SELF-TEST REGISTER (BIST)
Register Name Address Offset Power-up value Boot-load Attribute Size Built-in Self-Test 0Fh 00h External nvRAM/EPROM offset 04Fh D7, D5-0 Read Only, D6 as PCI bus write only 8 bits
The Built-In Self-Test (BIST) register permits the implementation of custom, user-specific diagnostics. This register has four fields as depicted in Figure 10. Bit 7, when set signifies that this device supports a built-in self test. When bit 7 is set, writing a 1 to bit 6 will commence the self test. In actuality, writing a 1 to bit 6 produces an interrupt to the Add-On interface. Bit 6 will remain set until cleared by a write operation to this register from the Add-On bus interface. When bit 6 is reset it is interpreted as completion of the self-test and an error is indicated by a non-zero value for the completion code (bits 3:0).
Figure 17. Built-In Self Test Register
7 X 6 0 5 0 4 0 3 X 2 X 1 X 0 X Bit Value User defined Completion Code (RO) Reserved (RO) Start BIST (WO) BIST Capable (RO)
Table 24. Built-In Self-Test Register
Bit 7 6 Description BIST Capable. This bit indicates that the Add-On device supports a built-in self-test when a one is returned. A zero should be returned if this self test feature is not desired. This field is read only from the PCI interface. Start BIST. Writing a 1 to this bit indicates that the self-test should commence. This bit can only be written when bit 7 is a 1. When bit 6 becomes set, an interrupt is issued to the Add-On interface. Other than through the reset pin, Bit 6 can only be cleared by a write to this element from the Add-On bus interface as outlined in Section 6.5. The PCI bus specification requires that this bit be cleared within 2 seconds after being set, or the device will be failed. Reserved. These bits are reserved. This field will always return zeros. Completion Code. This field provides a method for detailing a device-specific error. It is considered valid when the Start BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion code indicates successful completion.
5:4 3:0
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BASE ADDRESS REGISTERS (BADR)
Register Name Address Offset Power-up value Boot-load Attribute Size Base Address 10h, 14h, 18h, 1Ch, 20h, 24h FFFFFFC1h for offset 10h; 00000000h for all others External nvRAM offset 050h, 54h, 58h, 5Ch, 60h (BADR0-4) high bits Read/Write; low bits Read Only 32 bits
BADR5 register is not implemented and will return all 0's.
Determining Base Address Size
The address space defined by a given base address register is determined by writing all 1s to a given base address register from the PCI bus and then reading that register back. The number of 0s returned starting from D4 for memory space and D2 for I/O space toward the high-order bits reveals the amount of address space desired. Tables 23 and 24 list the possible returned values and their corresponding size for both memory and I/O, respectively. Included in the table are the nvRAM/EPROM boot values which correspond to a given assigned size. A register returning all zeros is disabled.
Assigning the Base Address
The base address registers provide a mechanism for assigning memory or I/O space for the Add-On function. The actual location(s) the Add-On function is to respond to is determined by first interrogating these registers to ascertain the size or space desired, and then writing the high-order field of each register to place it physically in the system's address space. Bit zero of each field is used to select whether the space required is to be decoded as memory (bit 0 = 0) or I/O (bit 0 = 1). Since this PCI controller has 16 DWORDs of internal operating registers, the Base Address Register at offset 10h is assigned to them. The remaining five base address registers can only be used by bootloading them from the external nvRAM interface.
Figure 18. Base Address Register -- Memory
31 30 29 4 3 X
After a base address has been sized as described in the preceding paragraph, the region associated with that base address register (the high order one bits) can physically locate it in memory (or I/O) space. For example, the first base address register returns FFFFFFC1h indicating an I/O space (D0=1) and is then written with the value 00000300h. This means that the controller's internal registers can be selected for I/O addresses between 00000300h through 0000033Fh, in this example. The base address value must be on a natural binary boundary for the required size (example 300h, 340h, 380h etc.; 338h would not be allowable).
2 X
1 X
0 X
Bit Value Memory Space0 = Memory Indicator (RO) 1 = I/O Type (RO) 00-locate anywhere (32) 01-below 1 MB 10-locate anywhere (64) 11-reserved Prefetchable (RO) Programmable (R/W)
See page 3-157
Base Address Register -- I/O
31 2 1 0 0 X Bit Value I/O Space Indicator (RO) Reserved (RO) Programmable (R/W)
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Table 25. Base Address Register -- Memory (Bit 0 = 0)
Bit 31:4 Description Base Address Location. These bits are used to position the decoded region in memory space. Only bits which return a 1 after being written as 1 are usable for this purpose. Except for Base Address Register 0, these bits are individually enabled by the contents sourced from the external boot memory. Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachable regions can only be located within the region altered through PCI bus memory writes. This bit, when set, also implies that all read operations will return the data associated for all bytes regardless of the Byte Enables. Memory space which cannot support this behavior should leave this bit in the zero state. For Base Addresses 1 through 4, this bit is set by the Reset pin and later initialized by the external boot memory (if present). Base Address Register 0 always has this bit set to 0. This bit is read only from the PCI interface. Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the space location is restricted to be within the first megabyte of memory space. The table below describes the encoding: Bits 21 00 01 10 11 1 Region is 32 bits wide and can be located anywhere in 32 bit memory space. Region is 32 bits wide and must be mapped below the first MByte of memory space. Region is 64 bits wide and can be mapped anywhere within 64 bit memory space. (Not supported by this controller.) Reserved. (Not supported by this controller.) Description
3
2:1
The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The only meaningful option is whether it is desired to position memory space anywhere within 32-bit memory space or restrain it to the first megabyte. For Base Addresses 1 through 5, this bit is set by the reset pin and later initialized by the external boot memory (if present). Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space and the remaining bits in the base address register are defined as shown in Table 22a.
0
Base Address Register -- I/O (Bit 0 = 1)
Bit 31:2 Description Base Address Location. These bits are used to position the decoded region in I/O space. Only bits which return a "1" after being written as "1" are usable for this purpose. Except for Base Address 0, these bits are individually enabled by the contents sourced from the external boot memory (EPROM or nvRAM). Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for the entire register location, bits 31 through 0). Space Indicator = 1. When one this bit identifies a base address region as an I/O space and the remaining bits in the base address register have the definition as shown in Table 11b.
1 0
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Table 26. Read Response (Memory Assigned) to an All-Ones Write Operation to a Base Address Register
Response 00000000h FFFFFFF0h FFFFFFE0h FFFFFFC0h FFFFFF80h FFFFFF00h FFFFFE00h FFFFFC00h FFFFF800h FFFFF000h FFFFE000h FFFFC000h FFFF8000h FFFF0000h FFFE0000h FFFC0000h FFF80000h FFF00000h FFE00000h FFC00000h FF800000h FF000000h FE000000h FC000000h F8000000h F0000000h E0000000h none - disabled 16 bytes (4 DWORDs) 32 bytes (8 DWORDs) 64 bytes (16 DWORDs) 128 bytes (32 DWORDs) 256 bytes (64 DWORDs) 512 bytes (128 DWORDs) 1K bytes (256 DWORDs) 2K bytes (512 DWORDs) 4K bytes (1K DWORDs) 8K bytes (2K DWORDs) 16K bytes (4K DWORDs) 32K bytes (8K DWORDs) 64K bytes (16K DWORDs) 128K bytes (32K DWORDs) 256K bytes (64K DWORDs) 512K bytes (128K DWORDs) 1M bytes (256K DWORDs) 2M bytes (512K DWORDs) 4M bytes (1M DWORDs) 8M bytes (2M DWORDs) 16M bytes (4M DWORDs) 32M bytes (8M DWORDs) 64M bytes (16M DWORDs) 128M bytes (32M DWORDs) 256M bytes (64M DWORDs) 512M bytes (128M DWORDs) Size in bytes [EPROM boot value]1 00000000h or BIOS missing2,3 FFFFFFF0h FFFFFFE0h FFFFFFC0h FFFFFF80h FFFFFF00h FFFFFE00h FFFFFC00h FFFFF800h FFFFF000h FFFFE000h FFFFC000h FFFF8000h FFFF0000h FFFE0000h FFFC0000h FFF80000h FFF00000h FFE00000h FFC00000h FF800000h FF000000h FE000000h FC000000h F8000000h F0000000h E0000000h
1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation). 2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space. See text for details. 3. BADR5 register is not implemented and will return all 0's.
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Table 27. Read Response (I/O Assigned) to an All-Ones write Operation to a Base Address Register
Response 00000000h FFFFFFFDh FFFFFFF9h FFFFFFF1h FFFFFFE1h FFFFFFC1h FFFFFF81h FFFFFF01h Size in bytes none - disabled 4 bytes (1 DWORDs) 8 bytes (2 DWORDs) 16 bytes (4 DWORDs) 32 bytes (8 DWORDs) 64 bytes (16 DWORDs) 128 bytes (32 DWORDs) 256 bytes (64 DWORDs) [EPROM boot value] 00000000h or BIOS missing1 FFFFFFFDh FFFFFFF9h FFFFFFF1h FFFFFFE1h FFFFFFC1h2 FFFFFF81h FFFFFF01h
1. BADR5 register is not implemented and will return all 0's. 2. Base Address Register 0 (at offset) 10h powers up as FFFFFFC1h. This default assignment allows usage without an external boot memory. Should an EPROM or nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFFC0h or FFFFFFC2h).
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EXPANSION ROM BASE ADDRESS REGISTER (XROM)
Register Name Address Offset Power-up value Boot-load Attribute Size Expansion ROM Base Address 30h 00000000h External nvRAM offset 70h bits 31:11, bit 0 Read/Write; bits 10:1 Read Only 32 bits
The expansion base address ROM register provides a mechanism for assigning a space within physical memory for an expansion ROM. Access from the PCI bus to the memory space defined by this register will cause one or more accesses to the S5935 controllers' external BIOS ROM (or nvRAM) interface. Since PCI bus accesses to the ROM may be 32 bits wide, repeated operations to the ROM are generated by the S5935 and the wider data is assembled internal to the S5935 controller and then transferred to the PCI bus by the S5935.
Figure 19. Expansion ROM Base Address Register
31 11 10 0 1 0 0 Bit Value Address Decode Enable (RW) 0=Disabled 1=Enabled Reserved (RO) Programmable (R/W)
Table 28. Expansion ROM Base Address Register
Bit 31:11 Description Expansion ROM Base Address Location. These bits are used to position the decoded region in memory space. Only bits which return a 1 after being written as 1 are usable for this purpose. These bits are individually enabled by the contents sourced from the external boot memory (EPROM or nvRAM). The desired size for the ROM memory is determined by writing all ones to this register and then reading back the contents. The number of bits returned as zeros, in order from least significant to most significant bit, indicates the size of the expansion ROM. This controller limits the expansion ROM area to 64K bytes. The allowable returned values after all ones are written to this register are shown in Table 26. Reserved. All zeros. Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit. When this bit is set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is required that the PCI command register also have the memory decode enabled for this bit to have an effect.
10:1 0
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Table 29. Read Response to Expansion ROM Base Address Register (after all-ones written)
Response 00000000h FFFFF801h FFFFF001h FFFFE001h FFFFC001h FFFF8001h FFFF0001h none - disabled 2K bytes (512 DWORDs) 4K bytes (1K DWORDs) 8K bytes (2K DWORDs) 16K bytes (4K DWORDs) 32K bytes (8K DWORDs) 64K bytes (16K DWORDs) Size in bytes [EPROM boot value] 00000000h or BIOS missing FFFFF801h FFFFF001h FFFFE001h FFFFC001h FFFF8001h FFFF0001h
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INTERRUPT LINE REGISTER (INTLN)
Register Name Address Offset Power-up value Boot-load Attribute Size Interrupt Line 3Ch FFh External nvRAM offset 7Ch Read/Write 8 bit
This register indicates the interrupt routing for the S5935 controller. The ultimate value for this register is system-architecture specific. For x86 based PCs, the values in this register correspond with the established interrupt numbers associated with the dual 8259 controllers used in those machines. In x86-based PC systems, the values of 0 to 15 correspond with the IRQ numbers 0 through 15, and the values from 16 to 254 are reserved. The value of 255 (the controller's default power-up value) signifies either "unknown" or "no connection" for the system interrupt. This register is bootloaded from the external boot memory, if present, and may be written by the PCI interface.
Figure 20. Interrupt Line Register
7
6
5
42
3 FFh
1
0
Bit Value
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INTERRUPT PIN REGISTER (INTPIN)
Register Name Address Offset Power-up value Boot-load Attribute Size Interrupt Pin 3Dh 01h External nvRAM offset 7Dh Read Only 8 bits
This register identifies which PCI interrupt, if any, is connected to the controller's PCI interrupt pins. The allowable values are 0 (no interrupts), 1 (INTA#), 2 (INTB#), 3 (INTC#), and 4 (INTD#). The default powerup value assumes INTA#.
Figure 21. Interrupt Pin Register
7 0 6 0 5 0 42 0 3 0 X 1 X 0 X Bit Value Pin Number 0 0 0 None 0 0 1 INTA# 0 1 0 INTB# 0 1 1 INTC# 1 0 0 INTD# 1 0 1 Reserved 1 1 X Reserved Reserved (all zeroes-RO)
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MINIMUM GRANT REGISTER (MINGNT)
Register Name Address Offset Power-up value Boot-load Attribute Size Minimum Grant 3Eh 00h External nvRAM offset 7Eh Read Only 8 bits
This register may be optionally used by bus masters to specify how long a burst period the device needs. A value of zero indicates that the bus master has no stringent requirement. The units defined by the least significant bit are in 250-ns increments. This register is treated as "information only" and has no further implementation within this device. Values other than zero are possible when an external boot memory is used.
Figure 22. Minimum Grant Register
7 0 6 00 5 4 0 3 0 2 0 1 0 0 0 bit value Value x 250ns (RO) 00-no requirement 01-FFh
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MAXIMUM LATENCY REGISTER (MAXLAT)
Register Name Address Offset Power-up value Boot-load Attribute Size Maximum Latency 3Fh 00h External nvRAM offset 7Fh Read Only 8 bits
This register may be optionally used by bus masters to specify how often this device needs PCI bus access. A value of zero indicates that the bus master has no stringent requirement. The units defined by the least significant bit are in 250-ns increments. This register is treated as "information only" and has no further implementation within this device. Values other than zero are possible when an external boot memory is used.
Figure 23. Maximum Latency Register
7 0 6 00 5 4 0 3 0 2 0 1 0 0 0 bit value Value x 250ns (RO) 00-no requirement 01-FFh
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The PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space (I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communication between the PCI and Add-On buses. Data, software-defined commands and command
Table 30. Operation Registers -- PCI Bus
Address Offset 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch Abbreviation OMB1 OMB2 OMB3 OMB4 IMB1 IMB2 IMB3 IMB4 FIFO MWAR MWTC MRAR MRTC MBEF INTCSR MCSR Register Name Outgoing Mailbox Register 1 Outgoing Mailbox Register 2 Outgoing Mailbox Register 3 Outgoing Mailbox Register 4 Incoming Mailbox Register 1 Incoming Mailbox Register 2 Incoming Mailbox Register 3 Incoming Mailbox Register 4 FIFO Register port (bidirectional) Master Write Address Register Master Write Transfer Count Register Master Read Address Register Master Read Transfer Count Register Mailbox Empty/Full Status Interrupt Control/Status Register Bus Master Control/Status Register
parameters can be either exchanged through the mailboxes, transferred through the FIFO in blocks under program control, or transferred using the FIFOs under Bus Master control. Table 1 lists the PCI Bus Operation Registers.
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OUTGOING MAILBOX REGISTERS (OMB)
Register Names PCI Address Offset Power-up value Attribute Size Outgoing Mailboxes 1-4 00h, 04h, 08h, 0Ch XXXXXXXXh Read/Write 32 bits These four DWORD registers provide a method for sending command or parameter data to the Add-On system. PCI bus operations to these registers may be in any width (byte, word, or DWORD). Writing to these registers can be a source for Add-On bus interrupts (if desired) by enabling their interrupt generation through the use of the Add-On's interrupt control/status register.
INCOMING MAILBOX REGISTERS (IMB)
Register Names PCI Address Offset Power-up value Attribute Size Incoming Mailboxes 1-4 10h, 14h, 18h, 1Ch XXXXXXXXh Read Only 32 bits These four DWORD registers provide a method for receiving user defined data from the Add-On system. PCI bus read operations to these registers may be in any width (byte, word, or DWORD). Only read operations are supported. Reading from these registers can optionally cause an Add-On bus interrupt (if desired) by enabling their interrupt generation through the use of the Add-On's interrupt control/status register. Mailbox 4, byte 3 only exists as device pins on the S5935 devices when used with a serial nonvolatile memory.
FIFO REGISTER PORT (FIFO)
Register Name PCI Address Offset Power-up value Attribute FIFO Port 20h XXXXXXXXh Read/Write This location provides access to the bidirectional FIFO. Separate registers are used when reading from or writing to the FIFO. Accordingly, it is not possible to read what was written to this location. The FIFO registers are implicitly involved in all bus master operations and, as such, should not be accessed during active bus master transfers. When operating upon the FIFOs with software program transfers involving word or byte operations, the endian sequence of the FIFO should be established as described under FIFO Endian Conversion Management in order to preserve the internal FIFO data ordering and flag management. The FIFO's fullness may be observed by reading the master control-status register or MCSR register.
Size
32 bits
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PCI CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR)
Register Name PCI Address Offset Power-up value Attribute Size Master Write Address 24h 00000000h Read/Write 32 bits
Note: Applications which require a non-DWORD starting boundary will need to move the first few bytes under software program control (and without using the FIFO) to establish a DWORD boundary. After the DWORD boundary is established the S5935 can begin the task of PCI bus master data transfers. The Master Write Address Register is continually updated during the transfer process and will always be pointing to the next unwritten location. Reading of this register during a transfer process (done when the S5935 controller is functioning as a target, i.e. not a bus master) is permitted and may be used to monitor the progress of the transfer. During the address phase for bus master write transfers, the two least significant bits presented on the PCI bus pins AD[31:0] will always be zero. This identifies to the target memory that the burst address sequence will be in a linear order rather than in an Intel 486 or PentiumTM cache line fill sequence. Also, the PCI bus address bit A1 will always be zero when this controller is the bus master. This signifies to the target that the S5935 controller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. Under certain circumstances, MWAR can be accessed from the Add-On bus instead of the PCI bus. See AddOn Initiated Bus Mastering.
This register is used to establish the PCI address for data moving from the Add-On bus to the PCI bus during PCI bus memory write operations. It consists of a 30-bit counter with the low-order two bits hardwired as zeros. Transfers may be any non-zero byte length as defined by the transfer count register, MWTC, and must begin on a DWORD boundary. This DWORD boundary starting constraint is placed upon this controller's PCI bus master transfers so that byte lane alignment can be maintained between the S5935 controller's internal FIFO data path, the Add-On interface, and the PCI bus.
Figure 24. PCI Controlled Bus Master Write Address Register
31 2 1 0 0 0 Bit Value DWORD Address (RO) Write Transfer Address (R/W)
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PCI CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC)
Register Name PCI Address Offset Power-up value Attribute Size Master Write Transfer Count 28h 00000000h Read/Write 32 bits
The master write transfer count register is used to convey to the S5935 controller the actual number of bytes that are to be transferred. The value in this register is decremented with each bus master PCI write operation until the transfer count reaches zero. Upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to either the PCI or Add-On bus interface. Transfers which are not whole multiples of DWORDs in size result in a partial word ending cycle. This partial word ending cycle is possible since all bus master transfers for this controller are required to begin on a DWORD boundary. Under certain circumstances, MWTC can be accessed from the Add-On bus instead of the PCI bus. See AddOn Initiated Bus Mastering.
Figure 25. PCI Controlled Bus Master Write Transfer Count Register
31 00 26 25 0 Bit Value Transfer Count in Bytes (R/W) Reserved = O's (RO)
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PCI CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR)
Register Name PCI Address Offset Power-up value Attribute Size Master Read Address 2Ch 00000000h Read/Write 32 bits
Note: Applications which require a non-DWORD starting boundary will need to move the first few bytes under software program control (and without using the FIFO) to establish a DWORD boundary. After the DWORD boundary is established the S5935 can begin the task of PCI bus master data transfers. The Master Read Address Register is continually updated during the transfer process and will always be pointing to the next unread location. Reading of this register during a transfer process (done when the S5935 controller is functioning as a target--i.e., not a bus master) is permitted and may be used to monitor the progress of the transfer. During the address phase for bus master read transfers, the two least significant bits presented on the PCI bus AD[31:0] will always be zero. This identifies to the target memory that the burst address sequence will be in a linear order rather than in an Intel 486 or PentiumTM cache line fill sequence. Also, the PCI bus address bit A1 will always be zero when this controller is the bus master. This signifies to the target that the controller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. Under certain circumstances, MRAR can be accessed from the Add-On bus instead of the PCI bus.
This register is used to establish the PCI address for data moving to the Add-On bus from the PCI bus during PCI bus memory read operations. It consists of a 30-bit counter with the low-order two bits hardwired as zeros. Transfers may be any non-zero byte length as defined by the transfer count register, MRTC (Section 5.7) and must begin on a DWORD boundary. This DWORD boundary starting constraint is placed upon this controller's PCI bus master transfers so that byte lane alignment can be maintained between the S5935 controller's internal FIFO data path, the Add-On interface and the PCI bus.
Figure 26. PCI Controlled Bus Master Read Address Register
31 2 1 0 0 0 Bit Value DWORD Address (RO) Read Transfer Address (R/W)
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PCI CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC)
Register Name PCI Address Offset Power-up value Attribute Size Master Read Transfer Count 30h 00000000h Read/Write 32 bits
The master read transfer count register is used to convey to the PCI controller the actual number of bytes that are to be transferred. The value in this register is decremented with each bus master PCI read operation until the transfer count reaches zero. Upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to either the PCI or Add-On bus interface. Transfers which are not whole multiples of DWORDs in size result in a partial word ending cycle. This partial word ending cycle is possible since all bus master transfers for this controller are required to begin on a DWORD boundary. Under certain circumstances, MRTC can be accessed from the Add-On bus instead of the PCI bus.
Figure 27. PCI Controlled Bus Master Read Transfer Count Register
31 00 26 25 0 Bit Value Transfer Count in Bytes (R/W) Reserved = 0's (RO)
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MAILBOX EMPTY FULL/STATUS REGISTER (MBEF)
Register Name PCI Address Offset Power-up value Attribute Size Mailbox Empty/Full Status 34h 00000000h Read Only 32 bits
This register provides empty/full visibility of each byte within the mailboxes. The empty/full status for the Outgoing mailboxes is displayed on the low-order 16 bits and the empty/full status for the Incoming mailboxes is presented on the high-order 16 bits. A value of 1 signifies that a given mailbox has been written by one bus interface but has not yet been read by the corresponding destination interface. A PCI bus incoming mailbox is defined as one in which data travels from the AddOn bus into the PCI bus, and an outgoing mailbox is defined as one where data travels out from the PCI bus to the Add-On interface.
Figure 28. Mailbox Empty/Full Status Register
31 16 15 0 Bit Value Outgoing Mailbox Status (RO) Incoming Mailbox Status (RO)
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Table 31. Mailbox Empty/Full Status Register
Bit 31:16 Description Incoming Mailbox Status. This field indicates which incoming mailbox registers have been written by the Add-On interface but have not yet been read by the PCI bus. Each bit location corresponds to a specific byte within one of the four incoming mailboxes. A value of one for each bit signifies that the specified mailbox byte is full, and a value of zero signifies empty. The mapping of these status bits to bytes within each mailbox is as follows: Bit 31 = Incoming mailbox 4 byte 3 Bit 30 = Incoming mailbox 4 byte 2 Bit 29 = Incoming mailbox 4 byte 1 Bit 28 = Incoming mailbox 4 byte 0 Bit 27 = Incoming mailbox 3 byte 3 Bit 26 = Incoming mailbox 3 byte 2 Bit 25 = Incoming mailbox 3 byte 1 Bit 24 = Incoming mailbox 3 byte 0 Bit 23 = Incoming mailbox 2 byte 3 Bit 22 = Incoming mailbox 2 byte 2 Bit 21 = Incoming mailbox 2 byte 1 Bit 20 = Incoming mailbox 2 byte 0 Bit 19 = Incoming mailbox 1 byte 3 Bit 18 = Incoming mailbox 1 byte 2 Bit 17 = Incoming mailbox 1 byte 1 Bit 16 = Incoming mailbox 1 byte 0 15:00 Outgoing Mailbox Status. This field indicates which out going mail box registers have been written by the PCI bus interface but have not yet been read by the Add-On bus. Each bit location corresponds to a specific byte within one of the four outgoing mailboxes. A value of one for each bit signifies that the specified mailbox byte is full, and a value of zero signifies empty. The mapping of these status bits to bytes within each mailbox is as follows: Bit 15 = Outgoing mailbox 4 byte 3 Bit 14 = Outgoing mailbox 4 byte 2 Bit 13 = Outgoing mailbox 4 byte 1 Bit 12 = Outgoing mailbox 4 byte 0 Bit 11 = Outgoing mailbox 3 byte 3 Bit 10 = Outgoing mailbox 3 byte 2 Bit 09 = Outgoing mailbox 3 byte 1 Bit 08 = Outgoing mailbox 3 byte 0 Bit 07 = Outgoing mailbox 2 byte 3 Bit 06 = Outgoing mailbox 2 byte 2 Bit 05 = Outgoing mailbox 2 byte 1 Bit 04 = Outgoing Mailbox 2 byte 0 Bit 03 = Outgoing Mailbox 1 byte 3 Bit 02 = Outgoing Mailbox 1 byte 2 Bit 01 = Outgoing Mailbox 1 byte 1 Bit 00 = Outgoing Mailbox 1 byte 0
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INTERRUPT CONTROL/STATUS REGISTER (INTCSR)
Register Name PCI Address Offset Power-up value Attribute Size Interrupt Control and Status 38h 00000000h Read/Write (R/W), Read/ Write_One_Clear (R/WC) 32 bits
This register provides the method for choosing which conditions are to produce an interrupt on the PCI bus interface, a method for viewing the cause of the interrupt, and a method for acknowledging (removing) the interrupt's assertion. Interrupt sources: * * * * * * Write Transfer Terminal Count = zero Read Transfer Terminal Count = zero One of the Outgoing mailboxes (1,2,3 or 4) becomes empty One of the Incoming mailboxes (1,2,3 or 4) becomes full. Target Abort Master Abort
Figure 29. Interrupt Control/Status Register
Actual Interrupt 24 23 21 31 FIFO and Endian Control 0 16 15 14 0 12 Interrupt Selection 8 000 4 0 Bit Value Interrupt Source (R/W) Enable & Selection D4-D0 Outgoing Mailbox (Goes empty) D4=Enable Interrrupt D3-D2=Mailbox # 0 0 1 1 0=Mailbox 1=Mailbox 0=Mailbox 1=Mailbox 1 2 3 4
Interrupt Asserted (RO) Target Abort (R/WC) Master Abort (R/WC) Read Transfer Complete (R/WC) Write Transfer Complete (R/WC) Incoming Mailbox Interrupt (R/WC) Outgoing Mailbox Interrupt (R/WC)
D1-D0=Byte # 0 0 1 1 0=Byte 0 1=Byte 1 0=Byte 2 1=Byte 3
D12-D8 Incoming Mailbox (R/W) (Becomes full) D12=Enable Interrupt D11-D10=Mailbox 0 0 1 1 0=Mailbox 1=Mailbox 0=Mailbox 1=Mailbox 1 2 3 4
D9-D8=Byte # 0 0=Byte 0 0 1=Byte 1 1 0=Byte 2 1 1=Byte 3 Interrupt on Write Transfer Complete Interrupt on Read Transfer Complete
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Figure 30. FIFO Management and Endian Control Byte
31 30 29 28 27 26 25 24
OUTBOUND FIFO PCI ADD-ON DWORD TOGGLE 0 = BYTES 0-3 (DEFAULT) 1 = BYTE 4-7 (NOTE1)
0 0 1 1
0 1 0 1
NO CONVERSION (DEFAULT) 16 BIT ENDIAN CONV. 32 BIT ENDIAN CONV. 64 BIT ENDIAN CONV
FIFO ADVANCE CONTROL PCI INTERFACE 0 0 BYTE 0 (DEFAULT) 0 1 BYTE 1 1 0 BYTE 2 1 1 BYTE 3
INBOUND FIFO ADD-ON PCI DWORD TOGGLE 0 = BYTES 0-3 (DEFAULT) 1 = BYTE 4-7 1
FIFO ADVANCE CONTROL ADD-ON INTERFACE 0 0 BYTE 0 (DEFAULT) 0 1 BYTE 1 1 0 BYTE 2 1 1 BYTE 3
NOTE 1: D24 and D25 MUST BE ALSO "1"
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Table 32. Interrupt Control/Status Register
Bit 31:24 23 FIFO and Endian Control. Interrupt asserted. This read only status bit indicates that one or more of the four possible interrupt conditions is present. This bit is nothing more than the ORing of the interrupt conditions described by bits 19 through 16 of this register. Reserved. Always zero. Target Abort. This bit signifies that an interrupt has been generated due to the S5935 encountering a target abort during a PCI bus cycle while the S5935 was the current bus master. This bit operates as read or write one clear. A write to this bit with the data of "one" will cause this bit to be reset, a write to this bit with the data of "zero" will not change the state of this bit. Master Abort. This bit signifies that an interrupt has been generated due to the S5935 encountering a Master Abort on the PCI bus. A master abort occurs when there is no target response to a PCI bus cycle. This bit operates as read or write one clear. A write to this bit with the data of "one" will cause this bit be reset, a write to this bit with the data of "zero" will not change the state of this bit. Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completion of a PCI bus master operation involving the transfer of data from the PCI bus to the Add-On. This interrupt will occur when the Master Read Transfer Count register reaches zero. This bit operates as read or write one clear. A write to this bit with the data of "one" will cause this bit to be reset; a write to this bit with the data of "zero" will not change the state of this bit. Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completion of a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. This interrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates as read or write one clear. A write to this bit with the data of "one" will cause this bit to be reset; a write to this bit with the data of "zero" will not change the state of this bit. Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of this register are written by the Add-On interface. This bit operates as read or write one clear. A write to this bit with the data of "one" will cause this bit to be reset; a write to this bit with the data as "zero" will not change the state of this bit. Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this register is read by the Add-On interface. This bit operates as read or write one clear. A write to this bit with the data of "one" will cause this bit to be reset; a write to this bit with the data of "zero" will not change the state of this bit. Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the read transfer count reaches zero. This bit is read/write. Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the write transfer count reaches zero. This bit is read/write. Reserved. Always zero. Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identified by bits 11 through 8 to produce a PCI interface interrupt. This bit is read/write. Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to be the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write. Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits 10 and 11 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/write. Reserved, Always zero. Description
22 21
20
19
18
17
16
15 14 13 12 11:10
9:8
7:5
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Table 32. Interrupt Control/Status Register (Continued)
Bit 4 3:2 Description Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailbox register identified by bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write. Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be the source for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write. Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits 3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/write.
1:0
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MASTER CONTROL/STATUS REGISTER (MCSR)
Register Name PCI Address Offset Power-up value Attribute Size32 bits Master Control/Status 3Ch 000000E6h Read/Write, Read Only, Write Only
The following PCI bus controls are available: * * * * * * * * * * * * * * * * * * * Write Priority over Read Read Priority over Write Write Transfer Enable Write master requests on 4 or more FIFO words available (full) Read transfer enable Read master requests on 4 or more FIFO available (empty) Assert reset to Add-On Reset Add-On to PCI FIFO flags Reset PCI to Add-On FIFO flags Reset mailbox empty full status flags Write external non-volatile memory PCI to Add-On FIFO FULL PCI to Add-On FIFO has four or more empty locations PCI to Add-On FIFO EMPTY Add-On to PCI FIFO FULL Add-On to PCI FIFO has four or more words loaded Add-On to PCI FIFO EMPTY PCI to Add-On Transfer Count = Zero Add-On to PCI Transfer Count = Zero
This register provides for overall control of this device. It is used to enable bus mastering for both data directions as well as providing a method to perform software resets.
The following PCI interface status flags are provided:
Figure 31. Bus Master Control/Status Register
Control 31 29 0 27 24 23 16 15 14 0 12 0 10 87 65 Status 0 Bit Value
nvRAM Access Ctrl
Reset Controls (R/WC) D27=Mailbox Flags Reset D26=Add-on to PCI FIFO Status Flags Reset D25=PCI to Add-on FIFO Status Flags Reset D24=Add-On Reset nv operation address/data Memory Read Multiple Enable = 1 Disable = 0 Read Transfer Control (R/W) (PCI memory reads) D14=Read Transfer Enable D13=FIFO Management Scheme D12=Read vs. Write Priority
FIFO STATUS (RO) D5=Add-on to PCI FIFO Empty D4=Add-on to PCI FIFO 4+ Words D3=Add-on to PCI FIFO Full D2=PCI to Add-on FIFO Empty D1=PCI to Add-on FIFO 4+Spaces D0=PCI to Add-on FIFO Full D7=Add-on to PCI Transfer Count equals zero (R0) D6=PCI to Add-on Transfer Count equals zero (R0) Write Transfer Control (R/W) (PCI memory writes) D10=Write Transfer Enable D9=FIFO Management Scheme D8=Write vs Read Priority
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Table 33. Bus Master Control/Status Register
Bit 31:29 Description nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory. Write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23 through 16. The sequence requires that the low-order address, high order address, and then a data byte are loaded in order. Bit 31 of this field acts as a combined enable and ready for the access to the external memory. D31 must be written to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to become zero (ready). D31 0 1 1 1 1 0 1 D30 X 0 0 1 1 X X D29 X 0 1 0 1 X X W/R W W W W W R R Inactive Load low address byte Load high address byte Begin write Begin read Ready Busy
Cautionary note: The nonvolatile memory interface is also available for access by the Add-On interface. Accesses by both the Add-On and PCI bus to the nv memory are not directly supported by the S5935 device. Software must be designed to prevent the simultaneous access of nv memory to prevent data corruption within the memory and provide for accurate data retrieval. 28 27 FIFO loop back mode. Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY). It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only. Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Add-On to PCI (Bus master memory writes) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus word flag to reset. It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only. PCI to Add-On FIFO Status Reset. Writing a one to this bit causes the PCI to Add-On (Bus master memory reads) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus words available flag to set. It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only. Add-On pin reset. Writing a one to this bit causes the reset output pin to become active. Writing a zero to this pin is necessary to remove the assertion of reset. This register bit is read/write. Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and 29 of this register to access the external non-volatile memory. The contents written are either low address, high address, or data as defined by bits 30 and 29. This register will contain the external non-volatile memory data when the proper read sequence for bits 31 through 29 is performed. Enable memory read multiple during S5935 bus mastering mode. Read Transfer Enable. This bit must be set to a one for S5935 PCI bus master read transfers to take place. Writing a zero to this location will suspend an active transfer. An active transfer is one in which the transfer count is not zero. Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain from requesting the PCI bus unless it has four or more vacant FIFO locations to fill. Once the controller is granted the PCI bus or is in possession of the bus due to the write channel, this constraint is not meaningful. When this bit is zero the controller will request the PCI bus if it has at least one vacant FIFO word.
26
25
24 23:16
15 14 13
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Table 33. Bus Master Control/Status Register
Bit 12 Description Read versus Write priority. This bit controls the priority of read transfers over write transfers. When set to a 1 with bit D8 as zero this indicates that read transfers always have priority over write transfers; when set to a one with D8 as one, this indicates that transfer priorities will alternate equally between read and writes. Reserved. Always zero. Write Transfer Enable. This bit must be set to a one for PCI bus master write transfers to take place. Writing a zero to this location will suspend an active transfer. An active transfer is one in which the transfer count is not zero. Write FIFO management scheme. When set to a one this bit causes the controller to refrain from requesting the PCI bus unless it has four or more FIFO locations filled. Once the S5935 controller is granted the PCI bus or is in possession of the bus due to the write channel, this constraint is not meaningful. When this bit is zero the controller will request the PCI bus if it has at least one valid FIFO word. Write versus Read priority. This bit controls the priority of write transfers over read transfers. When set to a one with bit D12 as zero this indicates that write transfers always have priority over read transfers. This combination is not allowed, data integrity may be compromised. When set to a one with D12 as one, this indicates that transfer priorities will alternate equally between writes and reads. Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfer count is all zeros. PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfer count is all zeros. Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completely empty. Add-On to PCI 4+ words. This bit is a one when there are four or more FIFO words valid within the Add-On to PCI bus FIFO. Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full. PCI to Add-On FIFO Empty. This bit is a one when the PCI bus to Add-On FIFO is completely empty. PCI to Add-On FIFO 4+ spaces. This bit signifies that there are at least four empty words within the PCI to Add-On FIFO. PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full.
11 10 9
8
7 6 5 4 3 2 1 0
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ADD-ON BUS OPERATION REGISTERS
The Add-On bus interface provides access to 18 DWORDs (72 bytes) of data, control and status information. All of these locations are accessed by asserting the Add-On bus chip select pin (SELECT#) in conjunction with either the read or write control strobes (signal pin RD# or WR#). Access to the FIFO can also be achieved through use of the dedicated pins, RDFIFO# and WRFIFO#. The dedicated pins for control of the FIFO are provided to optionally implement Direct Memory Access (DMA) on the Add-On bus, or to connect with an external FIFO. This register group represents the primary method for communication between the Add-On and PCI buses
Table 34. Operation Registers -- Add-On Interface
Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 58h 5Ch Abbreviation AIMB1 AIMB2 AIMB3 AIMB4 AOMB1 AOMB2 AOMB3 AOMB4 AFIFO MWAR1 APTA APTD MRAR1 AMBEF AINT AGCSTS MWTC1 MRTC1 Register Name Add-On Incoming Mailbox Register #1 Add-On Incoming Mailbox Register #2 Add-On Incoming Mailbox Register #3 Add-On Incoming Mailbox Register #4 Add-On Outgoing Mailbox Register #1 Add-On Outgoing Mailbox Register #2 Add-On Outgoing Mailbox Register #3 Add-On Outgoing Mailbox Register #4 Add-On FIFO port Bus Master Write Address Register Add-On Pass-Through Address Add-On Pass-Through Data Bus Master Read Address Register Add-On Mailbox Empty/Full Status Add-On Interrupt control Add-On General Control and Status Register Bus Master Write Transfer Count Bus Master Read Transfer Count
as viewed by the Add-On. The flexibility of this arrangement allows a number of user-defined software protocols to be built. For example, data, software assigned commands, and command parameters can be exchanged between the PCI and Add-On buses using either the mailboxes or FIFOs with or without handshaking interrupts. The register structure is very similar to that of the PCI operation register set. The major difference between the PCI bus and Add-On bus register complement are the absence of bus master control registers (4) on the Add-On side and the addition of two "pass-through" registers. Table 1 lists the Add-On interface registers.
1. See Add-On Initiated Bus Mastering.
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ADD-ON INCOMING MAILBOX REGISTERS (AIMBX)
Register Names Add-On Address Offset Power-up value Attribute Size Add-On Incoming Mailboxes 1-4 00h, 04h, 08h, 0Ch XXXXXXXXh Read Only 32 bits These four DWORD registers provide a method for receiving data, commands, or command parameters from the PCI interface. Add-On read operations to these registers may be in any width (byte, word, or DWORD). These registers are read-only. Writes to this address space have no effect. Reading from one of these registers can optionally cause a PCI bus interrupt (if desired) when the PCI interrupt control/ status register is properly configured.
ADD-ON OUTGOING MAILBOX REGISTERS (AOMBX)
Register Names Add-On Address Offset Power-up value Attribute Size Add-On Outgoing Mailboxes 1-4 10h, 14h, 18h, 1Ch XXXXXXXXh Read/Write 32 bits These four DWORD registers provide a method for sending data, commands, or command parameters or status to the PCI interface. Add-On write operations to these registers may be in any width (byte, word, or DWORD). These registers may also be read. Writing to one of these registers can optionally cause a PCI bus interrupt (if desired) when the PCI interrupt control/status register is properly configured. Mailbox 4, byte 3 only exists as device pins on the S5935 device when used with a serial nonvolatile memory. This byte is not available if a byte-wide nv memory is used.
ADD-ON FIFO REGISTER PORT (AFIFO)
Register Name Add-On Address Offset Power-up value Attribute Add-On FIFO Port 20h XXXXXXXXh Read/Write This location provides access to the bidirectional FIFO. Separate registers are involved when reading and writing to this location. Accordingly, it is not possible to read what was written to this location. The sequence of filling and emptying this FIFO is established by the PCI interface interrupt control and Status Register. The FIFO's fullness may be observed by reading the master control/status register or AGCSTS register Additionally, two signal pins are provided which reveal whether data is available (RDEMPTY) or space to write into the FIFO is available (WRFULL). These signals may be used to interface with user supplied DMA logic. Caution must be exercised when using these flags for FIFO transfers involving 64 bit endian conversion since the FIFO must operate on DWORD pairs.
Size
32 bits
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ADD-ON CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR)
Register Name Add-On Address Offset Power-up value Attribute Size Master Write Address 24h 00000000h Read/Write 32 bits
alignment can be maintained between the S5935 controller's internal FIFO data path, the Add-On interface, and the PCI bus. Note: Applications which require a non-DWORD starting boundary will need to move the first few bytes under software program control (and without using the FIFO) to establish a DWORD boundary. After the DWORD boundary is established the S5935 can begin the task of PCI bus master data transfers. The Master Write Address Register is continually updated during the transfer process and will always be pointing to the next unwritten location. Reading of this register during a transfer process (done when the S5935 controller is functioning as a target, i.e. not a bus master) is permitted and may be used to monitor the progress of the transfer. During the address phase for bus master write transfers, the two least significant bits presented on the PCI bus pins AD[31:0] will always be zero. This identifies to the target memory that the burst address sequence will be in a linear order rather than in an Intel 486 or PentiumTM cache line fill sequence. Also, the PCI bus address bit A1 will always be zero when this controller is the bus master. This signifies to the target that the S5935 controller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation.
This register is only accessible when Add-On initiated bus mastering is enabled. This register is used to establish the PCI address for data moving from the Add-On bus to the PCI bus during PCI bus memory write operations. It consists of a 30-bit counter with the low-order two bits hardwired as zeros. Transfers may be any non-zero byte length as defined by the transfer count register, MWTC and must begin on a DWORD boundary. This DWORD boundary starting constraint is placed upon this controller's PCI bus master transfers so that byte lane
Figure 32. Add-On Controlled Bus Master Write Address Register
31 2 1 0 0 0 Bit Value DWORD Address (RO) Write Transfer Address (R/W)
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ADD-ON PASS-THRU ADDRESS REGISTER (APTA)
Register Name Add-On Address Offset Power-up value Attribute Size Add-On Pass-Thru Address This register is employed when a response is desired when one of the Base address decode regions is selected during an active PCI bus cycle. When one of the base address decode registers 1-4 encounters a PCI bus cycle which selects the region defined by it, this device latches that current cycle's active address and asserts the signal PTATN# (Pass-Thru Attention). Wait states are generated on the PCI bus until either data is transferred or the PCI bus cycle is aborted by the initiator. This register provides a method for "live" data (registered) transfers. Intended uses include the emulating of other hardware as well as enabling the connection of existing external hardware to interface to the PCI bus through the S5935.
28h
XXXXXXXXh Read Only 32 bits
ADD-ON PASS-THRU DATA REGISTER (APTD)
Register Name Add-On Address Offset Power-up value Attribute Size Add-On Pass-Thru Data 2Ch XXXXXXXXh Read/Write 32 bits This register, along with APTA described above, is employed when a response is desired should one of the Base address decode regions become selected during an active PCI bus cycle. When one of the base address decode registers 1-4 encounters a PCI bus cycle which selects the region defined by it, the APTA register will contain that current cycle's active address and the device asserts the signal PTATN# (Pass-Thru ATentioN). Wait states are generated on the PCI bus until this register is read (PCI bus writes) or this register is written (PCI bus reads).
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ADD-ON CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR)
Register Name Add-On Address Offset Power-up value Attribute Size Master Read Address 30h 00000000h Read/Write 32 bits
Note: Applications which require a non-DWORD starting boundary will need to move the first few bytes under software program control (and without using the FIFO) to establish a DWORD boundary. After the DWORD boundary is established the S5935 can begin the task of PCI bus master data transfers.
This register is only accessible when Add-On initiated bus mastering is enabled. This register is used to establish the PCI address for data moving to the Add-On bus from the PCI bus during PCI bus memory read operations. It consists of a 30-bit counter with the low-order two bits hardwired as zeros. Transfers may be any non-zero byte length as defined by the transfer count register, MRTC and must begin on a DWORD boundary. This DWORD boundary starting constraint is placed upon this controller's PCI bus master transfers so that byte lane alignment can be maintained between the S5395X controller's internal FIFO data path, the Add-On interface and the PCI bus.
The Master Read Address Register is continually updated during the transfer process and will always be pointing to the next unread location. Reading of this register during a transfer process (done when the S5935 controller is functioning as a target--i.e., not a bus master) is permitted and may be used to monitor the progress of the transfer. During the address phase for bus master read transfers, the two least significant bits presented on the PCI bus AD[31:0] will always be zero. This identifies to the target memory that the burst address sequence will be in a linear order rather than in an Intel 486 or PentiumTM cache line fill sequence. Also, the PCI bus address bit A1 will always be zero when this controller is the bus master. This signifies to the target that the controller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. Under certain circumstances, MRAR can be accessed from the Add-On bus instead of the PCI bus.
Figure 33. Add-On Controlled Bus Master Read Address Register
31 2 1 0 0 0 Bit Value DWORD Address (RO) Read Transfer Address (R/W)
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ADD-ON EMPTY/FULL STATUS REGISTER (AMBEF)
Register Name Add-On Address Offset Power-up value Attribute Size Add-On Mailbox Empty/Full Status 34h 00000000h Read Only 32 bits
This register provides empty/full visibility of each byte within the mailboxes. The empty/full status for the Outgoing mailboxes are displayed on the high order 16 bits and the empty/full status for the incoming mailboxes are presented on the low order 16 bits. A value of one signifies that a given mailbox had been written by the sourcing interface but had not yet been read by the corresponding destination interface. An incoming mailbox is defined as one in which data travels from the PCI bus into the Add-On bus and an outgoing mailbox is defined as one where data goes OUT from the Add-On bus to the PCI interface.
Figure 34. Add-On Mailbox Empty/Full Status Register
31 16 15 0 Bit Value Incoming Mailbox Status (RO) Outgoing Mailbox Status (RO)
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Table 35. Add-On Mailbox Empty/Full Status Register
Bit 31:16 Description Outgoing Mailbox Status. This field indicates which outgoing mailbox registers have been written by the Add-On bus interface but have not yet been read by the PCI bus. Each bit location corresponds to a specific byte within one of the four outgoing mailboxes. A value of one for each bit signifies that the specified mailbox byte is full, a value of zero signifies empty. The mapping of these status bits to bytes within each mailbox is as follows: Bit 31 = Outgoing mailbox 4 byte 3 Bit 30 = Outgoing mailbox 4 byte 2 Bit 29 = Outgoing mailbox 4 byte 1 Bit 28 = Outgoing mailbox 4 byte 0 Bit 27 = Outgoing mailbox 3 byte 3 Bit 26 = Outgoing mailbox 3 byte 2 Bit 25 = Outgoing mailbox 3 byte 1 Bit 24 = Outgoing mailbox 3 byte 0 Bit 23 = Outgoing mailbox 2 byte 3 Bit 22 = Outgoing mailbox 2 byte 2 Bit 21 = Outgoing mailbox 2 byte 1 Bit 20 = Outgoing mailbox 2 byte 0 Bit 19 = Outgoing mailbox 1 byte 3 Bit 18 = Outgoing mailbox 1 byte 2 Bit 17 = Outgoing mailbox 1 byte 1 Bit 16 = Outgoing mailbox 1 byte 0 Incoming Mailbox Status. This field indicates which incoming mailbox registers have been written by the PCI bus but not yet been read by the Add-On interface. Each bit location corresponds to a specific byte within one of the four incoming mailboxes. A value of one for each bit signifies that the specified mailbox byte is full, a value of zero signifies empty. The mapping of these status bits to bytes within each mailbox is as follows: Bit 15 = Incoming mailbox 4 byte 3 Bit 14 = Incoming mailbox 4 byte 2 Bit 13 = Incoming mailbox 4 byte 1 Bit 12 = Incoming mailbox 4 byte 0 Bit 11 = Incoming mailbox 3 byte 3 Bit 10 = Incoming mailbox 3 byte 2 Bit 9 = Incoming mailbox 3 byte 1 Bit 8 = Incoming mailbox 3 byte 0 Bit 7 = Incoming mailbox 2 byte 3 Bit 6 = Incoming mailbox 2 byte 2 Bit 5 = Incoming mailbox 2 byte 1 Bit 4 = Incoming mailbox 2 byte 0 Bit 3 = Incoming mailbox 1 byte 3 Bit 2 = Incoming mailbox 1 byte 2 Bit 1 = Incoming mailbox 1 byte 1 Bit 0 = Incoming mailbox 1 byte 0
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ADD-ON INTERRUPT CONTROL/STATUS REGISTER (AINT)
Register Name Add-On Address Offset Power-up value Attribute Size Add-On Interrupt Control and Status 38h 00000000h Read/Write, Read/Write_One_Clear 32 bits
This register provides the method for choosing which conditions are to produce an interrupt on the Add-On bus interface, a method for viewing the cause for the interrupt, and a method for acknowledging (removing) the interrupt's assertion. Interrupt sources: * * * * * * One of the Incoming mailboxes (1,2,3 or 4) becomes full. One of the Outgoing mailboxes (1,2,3 or 4) becomes empty. Built-in self test issued. Write Transfer Count = zero Read Transfer Count = zero Target/Master Abort
Figure 35. Add-On Interrupt Control/Status Register
31
Interrupt Status 24 23 21 201918 17 16 1514 00000000 0 0
12
Interrupt Selection 8 4 000
0 Bit Value Interrupt Source (R/W) Enable & Selection D4-D0 Incoming Mailbox (Becomes Full) D4=Enable Interrrupt
Interrupt Asserted (RO) Bus Mastering Error Interrupt (R/WC) BIST (R/WC) Read Transfer Complete (R/WC) Write Transfer Complete (R/WC) Outgoing Mailbox Interrupt (R/WC) Incoming Mailbox Interrupt (R/WC)
D3-D2=Mailbox # 0 0 1 1 0=Mailbox 1=Mailbox 0=Mailbox 1=Mailbox 1 2 3 4
D0-D1=Byte # 0 0 1 1 0=Byte 0 1=Byte 1 0=Byte 2 1=Byte 3
D12-D8 Outgoing Mailbox (R/W) (Goes empty) D12=Enable Interrupt D11-D10=Mailbox 0 0 1 1 0=Mailbox 1=Mailbox 0=Mailbox 1=Mailbox 1 2 3 4
Interrupt on Write Transfer Complete Interrupt on Read Transfer Complete
D9-D8=Byte # 0 0=Byte 0 0 1=Byte 1 1 0=Byte 2 1 1=Byte 3
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Table 36. Interrupt Control/Status Register
Bit 31:24 23 22 21 Reserved. Always zero. Interrupt asserted. This read-only status bit indicates that one or more interrupt conditions is present. This bit is nothing more than the ORing of the interrupt conditions described by bits, 20, 17 and 16 of this register. Reserved. Always zero. Master/Target Abort. This bit signifies that an interrupt has been generated due to the S5935 encountering a Master or Target abort during an S5935 initiated PCI bus cycle. This bit operates as read or write one clear. Writing a one to this bit causes it to be cleared. Writing a zero to this bit does nothing. BIST. Built-In Self-Test interrupt. This interrupt occurs when a self test is initiated by the PCI interface writing of the BIST configuration register. This bit will stay set until cleared by writing a one to this location. Self test completion codes may be passed to the PCI BIST register by writing to the AGCSTS register. Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completion of a PCI bus master operation involving the transfer of data from the PCI bus to the Add-On. This interrupt will occur when the Master Read Transfer Count register reaches zero. This bit operates as read or write one clear. A write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completion of a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. This interrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates as read or write one clear. A write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. Outgoing Mailbox Interrupt. This bit sets when the mailbox selected by bits 12 through 8 of this register is read by the PCI interface. This bit operates as read or write one clear. A write to this bit with the data as one will cause this bit to be reset; a write to this bit with the data as zero will not change the state of this bit. Incoming Mailbox Interrupt. This bit sets when the mailbox selected by bits 4 through 0 of this register are written by the PCI interface. This bit operates as read or write one clear. A write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data as zero will not change the state of this bit. Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the read transfer count reaches zero. This bit is read/write. Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the write transfer count reaches zero. This bit is read/write. Reserved. Always zero. Enable outgoing mailbox interrupt. This bit allows a read by the PCI of the outgoing mailbox register identified by bits 11 through 8 to produce an Add-On interface interrupt. This bit is read/write. Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be the source for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write. Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits 11 and 10 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/write. Reserved. Always zero. Enable incoming mailbox interrupt. This bit allows a write from the PCI bus to the incoming mailbox register identified by bits 3 through 0 to produce an Add-On interface interrupt. This bit is read/write. Description
20
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18
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16
15 14 13 12 11:10
9:8
7:5 4
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Table 36. Interrupt Control/Status Register (Continued)
Bit 3:2 Description Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to be the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write. Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits 3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 2, and so on.
1:0
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ADD-ON GENERAL CONTROL/STATUS REGISTER (AGCSTS)
Register Name Add-On Address Offset Add-On General Control and Status 3Ch 000000F4h (PCI initiated bus mastering) 00000034h (Add-On initiated bus mastering) Read/Write, Read Only, Write Only 32 bits
This register provides for overall control of the Add-On portion of this device. It is used to provide a method to perform software resets of the mailbox and FIFO flags. The following Add-On controls are provided: * * * * * * * * * * Reset PCI to Add-On FIFO flags Reset Add-On to PCI FIFO flags Reset mailbox empty full status flags Write/read external non-volatile memory. Add-On to PCI FIFO FULL Add-On to PCI FIFO has four or more empty locations Add-On to PCI FIFO EMPTY PCI to Add-On FIFO FULL PCI to Add-On FIFO has four or more words loaded PCI to Add-On FIFO EMPTY
Power-up value
The following status flags are provided to the Add-On:
Attribute Size
Figure 36. Add-On General Control/Status Register
31 292827 2524 23 0 16 15 12 11 0 75 6 0 Bit Value
nvRAM Access Ctrl Transfer Count Enable Reset Controls D27=Mailbox Flags D26=PCI to Add-on FIFO Status Flags D25=Add-on to PCI FIFO Status Flags nv operation address/data
FIFO STATUS (RO) D5=PCI to Add-on FIFO Empty D4=PCI to Add-on 4+ Spaces D3=PCI to Add-on FIFO Full D2=Add-on to PCI FIFO Empty D1=Add-on to PCI FIFO 4+ Words D0=Add-on to PCI FIFO Full D6=Read Transfer Count Equals Zero (RO) D7=Write Transfer Count Equals Zero (RO) BIST Condition Code(R/W)
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Table 37. Add-On General Control/Status Register
Bit 31:29 Description nvRAM/EPROM Access Control. This field provides a method for access to the optional, external non-volatile memory. Write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23 through 16. The sequence requires that the low-order address, high-order address, and then a data byte be loaded in order. Bit 31 of this field acts as an enable/clock and ready for the access to the external memory. D31 must be written to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to become zero (ready). D31 0 1 1 1 1 0 1 D30 X 0 0 1 1 X X D29 X 0 1 0 1 X X W/R W W W W W R R Inactive Load low address byte Load high address byte Begin write Begin read Ready Busy
Cautionary note: The non-volatile memory interface is also available for access by the PCI bus interface. Accesses by both the Add-On and PCI bus to the nv memory are not directly supported by this component. Software must be designed to prevent the simultaneous access of nv memory to prevent data corruption within the memory and provide for accurate data retrieval. 28 27 Transfer Count Enable. When set, transfer counts are used for Add-On initiated bus master transfers. When clear, transfer counts are ignored. Mailbox Flag Reset. Writing a 1 to this bit causes all mailbox status flags to become reset (EMPTY). It is not necessary to write this bit as 0 because it is used internally to produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only. Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Outbound (Bus master writes) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus words available flag to reset. It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Since reading of this bit would always produce zeros, this bit is write only. PCI to Add-On FIFO Status Reset. Writing a 1 to this bit causes the Inbound (Bus master reads) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus spaces flag to set. It is not necessary to write this bit as 0 because it is used internally to produce a reset pulse. Since reading of this bit would always produce zeros, this bit is write only. Reserved. Always zero. Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and 29 of this register to access the external non-volatile memory. The contents written are either low address, high address, or data as defined by bits 30 and 29. This register will contain the external non-volatile memory data when the proper read sequence for bits 31 through 29 is performed. BIST condition code. This field is directly connected to the PCI configuration self test register. Bit 15 through 12 maps with the BIST register bits 3 through 0, respectively. Reserved. Always zero. Add-On to PCI Transfer Count Equal Zero (RO). This bit as a one signifies that the write transfer count is all zeros. Only when Add-On initiated bus mastering is enabled.
26
25
24 23:16
15:12 11:8 7
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Table 37. Add-On General Control/Status Register (Continued)
Bit 6 5 4 3 2 1 0 Description PCI to Add-On Transfer Count Equals Zero (RO). This bit as a one signifies that the read transfer count is all zeros. Only when Add-On initiated bus mastering is enabled. PCI to Add-On FIFO Empty. This bit is a 1 when the PCI to Add-On FIFO is empty. PCI to Add-On FIFO 4+ spaces. This bit is a 1 when there are four or more open spaces in the PCI to Add-On FIFO. PCI to Add-On FIFO Full. This bit is a 1 when the PCI to Add-On FIFO is full. Add-On to PCI FIFO Empty. This bit is a 1 when the Add-On to PCI FIFO is empty. Add-On PCI FIFO 4+ words. This bit is a 1 when there are four or more full locations in the Add-On to PCI FIFO. Add-On to PCI FIFO Full. This bit is a 1 when the Add-On to PCI FIFO is full.
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ADD-ON CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC)
Register Name Add-On Address Offset Power-up value Attribute Size Master Write Transfer Count 58h 00000000h Read/Write 32 bits
This register is only accessible when Add-On initiated bus mastering is enabled. The master write transfer count register is used to convey to the S5935 controller the actual number of bytes that are to be transferred. The value in this register is decremented with each bus master PCI write operation until the transfer count reaches zero. Upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to either the PCI or Add-On bus interface. Transfers which are not whole multiples of DWORDs in size result in a partial word ending cycle. This partial word ending cycle is possible since all bus master transfers for this controller are required to begin on a DWORD boundary.
Figure 37. Add-On Controlled Bus Master Write Transfer Count Register
31 00
26
25
0
Bit Value Transfer Count in Bytes (R/W) Reserved = O's (RO)
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ADD-ON CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC)
Register Name Add-On Address Offset Power-up value Attribute Size Master Read Transfer Count 5Ch 00000000h Read/Write 32 bits
This register is only accessible when Add-On initiated bus mastering is enabled. The master read transfer count register is used to convey to the PCI controller the actual number of bytes that are to be transferred. The value in this register is decremented with each bus master PCI read operation until the transfer count reaches zero. Upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to either the PCI or Add-On bus interface. Transfers which are not whole multiples of DWORDs in size result in a partial word ending cycle. This partial word ending cycle is possible since all bus master transfers for this controller are required to begin on a DWORD boundary.
Figure 38. Add-On Controlled Bus Master Read Transfer Count Register
31 00
26 25
0 Bit Value Transfer Count in Bytes (R/W) Reserved = 0's (RO)
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INITIALIZATION
All PCI bus agents and bridges are required to implement PCI Configuration Registers. When multiple PCI devices are present, these registers must be unique to each device in the system. The specified PCI procedure for uniquely selecting a device's configuration space involves a dedicated signal, called IDSEL, connected to each motherboard PCI bus device and PCI slot. The host executes configuration cycles after reset to each device on the PCI bus. The configuration registers provide information on PCI agent operation and memory or I/O space requirements. These allow the PCI BIOS to enable the device and locate it within system memory or I/O space. After a PCI reset, the S5935 can be configured for a specific application by downloading device setup information from an external non-volatile memory into the device Configuration Registers. The S5935 can also be used in a default configuration, with no external boot device. When using a non-volatile boot memory to customize operation, 64 bytes are required for S5935 setup information. The rest of the boot device may be used to implement an Expansion BIOS, if desired. Some of the setup information is used to initialize the S5935 PCI Configuration Registers, other information is not downloaded into registers, but is used to define S5935 operation (FIFO interface, Pass-Thru operation, etc.). host CPU to the S5935 produce PCI bus wait states until one of the following events occurs: * The S5935 identifies that there is no valid boot memory (and default Configuration Register values are used). The S5935 finishes downloading all configuration information from a valid boot memory.
*
LOADING FROM BYTE-WIDE NV MEMORIES
The SNV input on the S5935 indicates what type of external boot-load device is present (if any). If SNV is tied low, a byte-wide nv memory is assumed. In this case, immediately after the PCI bus reset is deasserted, the address 0040h is presented on the nv memory interface address bus EA[15:0]. Eight PCI clocks later (240 ns at 33 MHz), data is read from the nv memory data bus EQ[7:0] and address 0041h is presented. After an additional eight PCI clocks, data is again read from EQ7:0. If both accesses read are all ones (FFh), it implies an illegal Vendor ID value, and the external nv memory is not valid or not present. In this situation, the AMCC default configuration values are used. If either of the accesses to address 0040h and 0041h contain zeros (not FFh), the next accesses are to locations 0050h, 0051h, 0052h, and 0053h. At these locations, the data must be C0h (or C1h or C2h), FFh, E8h, and 10h, respectively, for the external nv memory to be valid. Once a valid external nv memory has been recognized, it is read, sequentially, from location 0040h to 007Fh. The appropriate data is loaded into the PCI Configuration Registers as described in Chapter 4. Some of the boot device data is not downloaded into Configuration Registers, but is used to enable features and configure S5935 operation. Upon completion of this procedure, the boot-load sequence terminates and PCI configuration accesses to the S5935 are acknowledged with the PCI Target Ready (TRDY#) output. Table 1 lists the required nv memory contents for a valid configuration nv memory device.
PCI RESET
Immediately following the assertion of the PCI RST# signal, the Add-On reset output SYSRST# is asserted. Immediately following the deassertion of RST#, SYSRST# is deasserted. The Add-On reset output may be used to initialize state machines, reset Add-On microprocessors, or reset other Add-On logic devices. All S5935 Operation Registers and Configuration Registers are initialized to their default states at reset. The default values for the Configuration Registers may be overwritten with the contents of an external nv boot memory during device initialization, allowing a custom device configuration. Configuration accesses by the
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Table 38. Valid External Boot Memory Contents
Address 0040h-41h 0050h Data not FFFFh C2h, C1h or C0h Notes This is the location that the S5933 PCI Controller will load a customized vendor ID. (FFFFh is an illegal vendor ID.) This is the least significant byte of the region which initializes the base address register #0 of the S5933 configuration register (Section 3.11). A value of C1h assigns the 16 DWORD locations of the PCI operation registers into I/O space, a value of C0h defines memory space, a value of C2h defines memory space below 1 Mbyte. Required. Required. Required.
0051 0052h 0053h
FFh E8h 10h
LOADING FROM SERIAL NV MEMORIES SNV tied high indicates that a serial nv memory (or no external device) is present. When serial nv memories are used, data transfer is performed through a twowire, bidirectional data transfer protocol as defined by commercial serial EEPROM/Flash offerings. These devices have the advantages of low pin counts, small package size, and economical price. A serial nv memory is considered valid if the first serial accesses contain the correct per-byte acknowledgments (see Figure 3). If the serial per-byte acknowledgment is not observed, the S5935 determines that no external serial nv memory is present and the AMCC default Configuration Register values are used. Two pins are used to transfer data between the S5935 PCI controller and the external serial memory: a serial clock pin, SCL, and a serial data pin, SDA. The serial clock pin is an output from the S5935, and the serial data pin is bidirectional. The serial clock is derived by dividing the PCI bus clock by 512. This means that the frequency of the serial clock is approximately 65 kHz for a 33-MHz PCI bus clock. Note: When a serial boot device is used, EA9 is defined as a SCL divide by control pin. If EA9 = 1 then SCL = PCLK/512 If EA9 = 0 then SCL = PCLK/8 This pin should be pulled high. Communications with the serial memory involve several clock transitions. A start event signals the beginning of a transaction and is immediately followed
by an address transfer. Each address/data transfer consists of 8 bits of information followed by a 1-bit acknowledgment. When the exchange is complete, a stop event is issued. Figure 1 shows the unique relationship defining both a start and stop event. Figure 2 shows the required timing for address/data with respect to the serial clock. For random accesses, the sequence involves one clock to define the start of the sequence, eight clocks to send the slave address and read/write command, followed by a one-clock acknowledge, and so on. Figure 3 shows the sequence for a random write access requiring 29 serial clock transitions. At the clock speed for the S5935, this corresponds to one byte of data transferred approximately every 0.5 milliseconds. Read accesses may be either random or sequential. Random read access requires a dummy write to load the word address and require 39 serial clock transitions. Figure 4 shows the sequence for a random byte read. To initialize the S5935 controller's PCI Configuration Registers, the smallest serial device necessary is a 128 x 8 organization. Although the S5935 controller only requires 64 bytes, these bytes must begin at a 64byte address offset (0040h through 007Fh). This offset constraint permits the configuration image to be shared with a memory containing expansion BIOS code and the necessary preamble to identify an expansion BIOS. The largest serial device which may be used is 2 Kbytes.
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Figure 39. Serial Interface Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
Figure 40. Serial Interface Clock/Data Relationship
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
Figure 41. Serial Interface Byte Access -- Write
S T A R T
SLAVE R/W ADDRESS
WORD ADDRESS
DATA
S T O P * A C K
1010
0A
C K
A C K
Figure 42. Serial Interface Byte Access -- Read
S T A R T S T A R T A C K
SLAVE R/W ADDRESS
WORD ADDRESS
SLAVE R/W ADDRESS
DATA
S T O P * A C K
1010
0A
C K
1010
1A C K
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PCI BUS CONFIGURATION CYCLES
Cycles beginning with the assertion IDSEL and FRAME# along with the two configuration command states for C/BE[3:0] (configuration read or write) access an individual device's configuration space. During the address phase of the configuration cycle just described, the values of AD0 and AD1 identify if the access is a Type 0 configuration cycle or a Type 1 configuration cycle. Type 0 cycles have AD0 and AD1 equal to 0 and are used to access PCI bus agents. Type 1 configuration cycles are intended only for bridge devices and have AD0 as a 1 with AD1 as a 0 during the address phase. The S5935 PCI device is a bus agent (not a bridge) and responds only to a Type 0 configuration accesses. Figure 5 depicts the state of the AD bus during the address phase of a Type 0 configuration access. The S5935 controller does not support the multiple function numbers field (AD[10:8]) and only responds to the allzero function number value. The configuration registers for the S5935 PCI controller can only be ac cessed under the follow ing conditions: * IDSEL high (PCI slot unique signal which identifies access to configuration registers) along with FRAME# low. Address bits A0 and A1 are 0 (Identifies a Type 0 configuration access). Address bits A31-A11 are ignored. Address bits A8, A9, and A10 are 0 (Function number field of zero supported). Command bits, C/BE[3:0]# must identify a configuration cycle command (101X).
* * * *
Figure 6 describes the signal timing relationships for configuration read cycles. Figure 7 describes configuration write cycles.
Figure 43. PCI AD Bus Definition During a Type 0 Configuration Access
31 11 10 8 7 2 1 00 RESERVED FUNCTION NUMBER REGISTER NUMBER TYPE 0 0
00XXXXXX INTERNAL REGISTER ADDRESS (DEVICE ID, ETC.) ONLY 000 VALUE SUPPORTED BY THIS DEVICE.
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Figure 44. Type 0 Configuration Read Cycles
1 PCI CLOCK FRAME # AD [31:0] C/BE [3:0]# IRDY# TRDY# IDSEL DEVSEL#
(I) (T) (I) (I) (I) (T) ADDRESS CONFIG. READ CMD DATA BYTE ENABLES
2
3
4
NOTE
IF FRAME # STILL ASSERTED DURING CLOCK 2, CONTROLLER ASSERTS STOP# DURING 3 DRIVEN BY CONTROLLER DURING CLOCK 3
DRIVEN BY CONTROLLER DURING CLOCKS 2,3 +4
(I) (T)
DRIVEN BY CONTROLLER DURING CLOCKS 2,3 +4
SELECT CONDITION
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
Figure 45. Type 0 Configuration Write Cycles
1 PCI CLOCK FRAME # AD [31:0] C/BE [3:0]# IRDY# TRDY# IDSEL DEVSEL#
(I)
2
3
4
NOTE
FRAME # DEASSERTED IN CLOCK 2, SIGNIFIES ONLY ONE DATA PHASE
ADDRESS CONFIG WRITE CMD DATA BYTE ENABLES
(I) (I) (I) (T)
DRIVEN BY CONTROLLER DURING CLOCKS 2+3
(I) (T)
DRIVEN BY CONTROLLER DURING CLOCKS 2+3
SELECT CONDITION
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
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EXPANSION BIOS ROMS
This section provides an example of a typical PC-compatible expansion BIOS ROM. Address offsets 0040h through 007Fh represent the portion of the external nv memory used to boot-load the S5935 controller. Whether the expansion ROM is intended to be executTable 39. PC Compatible Expansion ROM
Byte Offset 0h 1h 2h 3h 7h-17h 18h-19h 20h-3Fh Byte Length 1 1 1 4 17h 2 32h 55h AAh var. var. var. var. var Binary Value Description BIOS ROM signature byte 1 BIOS ROM signature byte 2 Length in multiples of 512 bytes Entry point for INIT function. Reserved (application unique data) Pointer to PCI Data Structure (see Table 3) user-defined Example 55h AAh 01h
able code is determined by the contents of the first three locations (starting at offset 0h) and a byte checksum over the defined length. The defined length is specified in the byte at address offset 0002h. Table 2 lists each field location by its address offset, its length, its value, and description.
The following represents the boot-load image for the S5935 controller's PCI configuration register: 40h 42h 44h 45h 46h 48h 49h 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 58h 5Ch 60h 64h 2 2 1 1 2 1 3 1 1 1 1 1 1 1 1 4 4 4 4 4 [your vendor ID] [your device ID] not used [Bus Master Config.] not used [your revision ID] [your class code] not used [your latency timer #] [your header type] [self-test if desired] C0h, C1h or C2h FFh E8h 10h [base addr. #1] [base addr. #2] [base addr. #3] [base addr. #4] [base addr. #5] 00h 00h 80h or 00h C0h, C1h or C2h FFh E8h 10h xxxxxxxxh xxxxxxxxh xxxxxxxxh xxxxxxxxh xxxxxxxxh FF0000h 10e8h 4750h 00h 80h
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Table 39. PC Compatible Expansion ROM
Byte Offset 68h 70h 74h 7Ch 7Dh 7Eh 7Fh 80h -- (1FFh), or (2FFh), or (3FFh), etc. Byte checksum, location dependent on value for length field at offset 0002h. Byte Length 8 4 8 1 1 1 1 Binary Value not used [Expansion ROM base addr.] not used [Interrupt line] [Interrupt pin] [Min-Grant] [Max_lat] 0Ch 01h 00h 00h (example shows 32K bytes) FFFF8001h Description Example
application specific
A 16-bit pointer at location 18h of the PC expansion ROM identifies the start offset of the PCI data structure. The PCI data structure is shown in Table 3 and contains various vendor, product, and program evolutions. If a valid external nv memory is identified by the S5935, the PCI data structure is used to configure the S5935. The PCI data structure is not necessary for this device to operate. If no external nv memory is implemented, the S5935 boots with the default configuration values.
Table 40. PCI Data Structure
Byte Offset 0h 4h 6h 8h Ah Ch Dh 10h 12h 14h 15h 16h Byte Length 4 2 2 2 2 1 3 2 2 1 1 2 Binary Value `PCIR' var. var. var. var. var. var. var. var. var. var. 0000h
Note: If a serial BIOS ROM is used, the access time for large serial devices should be considered, since it may cause a lengthy system delay during initialization. For example, a 2-Kbyte serial device takes about 1 second to be read. Many systems, even when BIOS ROMs are ultimately shadowed into system RAM, may read this memory space twice (once to validate its size and checksum, and once to move it into RAM). Execution directly from a serial BIOS ROM, although possible, may be unacceptably slow.
Description Signature, the ASCII string `PCIR' where `P' is at offset 0, `C' at offset 1, and so on. Vendor Identification Device Identification Pointer to Vital Product Data PCI Data Structure Length (starts with signature field) PCI Data Structure Revision (=0 for this definition) Class Code Image Length Revision Level Code Type Indicator (bit D7=1 signifies "last image") Reserved
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PCI BUS INTERFACE
This section describes the various events which occur on the S5935 PCI bus interface. Since the S5935 controller functions as both a target (slave) and an initiator (master), signal timing detail is given for both situations this Section presents the signal relationships involved in performing basic read or write transfers on the PCI bus and also describes the different ways these cycles may complete. A data phase consists of at least one PCI clock. FRAME# is deasserted to indicate that the final data phase of a PCI cycle is occurring. Wait states may be added to any data phase (each wait state is one PCI clock). The PCI bus command presented on the C/BE[3:0]# pins during the address phase can represent 16 possible states. Table 1 lists the PCI commands and identifies those which are supported by the S5935 controller as a target and those which may be produced by the S5935 controller as an initiator. A "Yes" in the "Supported As Target" column in Table 1 indicates t he S5935 cont roller as serts the signal DEVSEL# when that command is issued along with the appropriate PCI address. Two commands are supported by the S5935 controller as an initiator: Memory Read and Memory Write. The completion or termination of a PCI cycle can be signaled in several ways. In most cases, the completion of the final data phase is indicated by the assertion of ready signals from both the target (TRDY#) and initiator (IRDY#) while FRAME# is inactive. In some cases, the target is not be able to continue or support a burst transfer and asserts the STOP# signal. This is referred to as a target disconnect. There are also cases where an addressed device does not exist, and the signal DEVSEL# never becomes active. When no DEVSEL# is asserted in response to a PCI cycle, the initiator is responsible for ending the cycle. This is referred to as a master abort. The bus is returned to the idle phase when both FRAME# and IRDY# are deasserted.
PCI BUS TRANSACTIONS
Because the PCI bus has multiplexed address/data pins, AD[31:0], each PCI bus transaction consists of two phases: Address and Data. An address phase is defined by the clock period when the signal FRAME# transitions from inactive (high) to active (low). During the address phase, a bus command is also driven by the initiator on signal pins C/BE[3:0]#. If the command indicates a PCI read, the clock cycle following the address phase is used to perform a "bus turn-around" cycle. A turn-around cycle is a clock period in which the AD bus is not driven by the initiator or the target device. This is used to avoid PCI bus contention. For a write command, a turn-around cycle is not needed, and the bus goes directly from the address phase to the data phase. All PCI bus transactions consist of an address phase (described above), followed by one or more data phases. The address phase is only one PCI clock long and the bus cycle information (address and command) is latched internally by the S5935. The number of data phases depends on how many data transfers are desired or are possible with a given initiator-target pair.
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Table 41. Supported PCI Bus Commands
C/BE[3:0]# 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Reserved Memory Read Line Memory Write & Invalidate Supported As Target No No Yes Yes No No Yes Yes No No Yes Yes Yes1 No Yes1 Yes2 Supported As Initiator No No No No No No Yes Yes No No No No No3 No No No
1. Memory Read Multiple and Read Line are treated as Memory Reads. 2. Memory Write & Invalidate commands are treated as Memory Writes. 3. Must be enabled by bit 15 MCSR.
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PCI BURST TRANSFERS
The PCI bus, by default, expects burst transfers to be executed. To successfully perform a burst transfer, both the initiator and target must order their burst address sequence in an identical fashion. There are two different ordering schemes: linear address incrementing and 80486 cache line fill sequencing. The exact ordering scheme for a bus transaction is defined by the state of the two least significant AD lines during the address phase. The decoding for these lines is shown below: regions defined by the Base Address Registers 1-4 may be bursts, if desired.
PCI Read Transfers
The S5935 responds to PCI bus memory or I/O read transfers when it is selected (target). As a PCI bus initiator, the S5935 controller may also produce PCI bus memory read operations. Figure 1 depicts the fastest burst read transfer possible for the PCI bus. The timings shown in Figure 1 are representative of the S5935 as a PCI initiator with a fast, zero-wait-state memory target. The signals driven by the S5935 during the transfer are FRAME#, C/ BE[3:0]#, and IRDY#. The signals driven by the target are DEVSEL# and TRDY#. AD[31:0] are driven by both the target and initiator during read transactions (only one during any given clock). Clock period 2 is a required bus turn-around clock which ensures bus contention between the initiator and target does not occur. Targets drive DEVSEL# and TRDY# after the end of the address phase (boundary of clock periods 1 and 2 of Figure 1). TRDY# is not driven until the target can provide valid data for the PCI read. When the S5935 becomes the PCI initiator, it attempts to perform sustained zero-wait state burst reads until one of the following occurs: * * * * * * The memory target aborts the transfer PCI bus grant (GNT#) is removed The PCI to Add-On FIFO becomes full A higher priority (Add-On to PCI) S5935 transfer is pending (if programmed for priority) The read transfer byte count reaches zero Bus mastering is disabled from the Add-On interface
AD[1:0] 00 01 10 11
Burst Order Linear sequence Reserved Cacheline Wrap Mode Reserved
The S5935 supports both the linear and the cache line burst ordering. When the S5935 controller is an initiator, it always employs a linear ordering. Some accesses to the S5935 controller (as a target) can not be burst transfers. For example, the S5935 does not allow burst transfers when accesses are made to the configuration or operation registers (including the FIFO as a target). Attempts to perform burst transfers to these regions cause STOP# to be asserted during the first data phase. The S5935 completes the initial data phase successfully, but asserting STOP# indicates that the next access needs to be a completely new cycle. Accesses to memory or I/O
Figure 46. Zero Wait State Burst Read PCI Bus Transfer (S5935 as Initiator)
12 PCI CLOCK FRAME # AD [31:0] C/BE [3:0]# IRDY# TRDY# DEVSEL#
(I) (I) ADDRESS BUS COMMAND (I) (I) (T) (T) (I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET (T) DATA (1) BYTE ENABLES (1) (T) DATA (2) BYTE EN (2) (T) DATA (3) BYTE EN (3)
3
45
6
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Read accesses from the S5935 operation registers (S5935 as a target) are shown in Figure 2. The S5935 conditionally asserts STOP# in clock period 3 if the initiator keeps FRAME# asserted during clock period 2 with IRDY# asserted (indicating a burst is being attempted). Wait states may be added by the initiator by not asserting the signal IRDY# during clock 3 and beyond. If FRAME# remains asserted, but IRDY# is not asserted, the initiator is just adding wait states, not necessarily attempting a burst. There is only one condition where accesses to S5935 operation registers do not return TRDY# but do assert STOP#. This is called a target-initiated termination or target disconnect and occurs when a read attempt is made to an empty S5935 FIFO. The assertion of STOP# without the assertion of TRDY# indicates that the initiator should retry the operation later. When burst read transfers are attempted to the S5935 operation registers, STOP# is asserted during the first data transfer to indicate to the initiator that no further transfers (data phases) are possible. This is a target initiated termination where the target disconnects after the first data transfer. Figure 3 shows the signal relationships during a burst read attempt to the S5935 operation registers.
Figure 47. Single Data Phase PCI Bus Read of S5935 Registers (S5935 as Target)
1 2 3 45
FRAME # AD [31:0]
(I) (I)
ADDRESS
(T)
DATA BYTE ENABLES
(I) C/BE [3:0]# IRDY# TRDY# DEVSEL# STOP# (I) (T) (T) (T)
BUS COMMAND
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
Figure 48. Burst PCI Bus Read Attempt to S5935 Registers (S5935 as Target)
1 PCI CLOCK FRAME # AD [31:0] C/BE [3:0]# IRDY# TRDY# DEVSEL# STOP# (I) (I)
ADDRESS BUS COMMAND
2
3
45
(T)
DATA BYTE ENABLES (1) BE (2)
(I) (I) (T) (T) (T)
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
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PCI Write Transfers
Write transfers on the PCI bus are one clock period shorter than read transfers. This is because the AD[31:0] bus does not require a turn-around cycle between the address and data phases. When the S5935 is accessed (target), it responds to a PCI bus memory or I/O transfers. As a PCI initiator, the S5935 controller can also execute PCI memory write operations. The timing diagram in Figure 4 represents an S5935 initiator PCI write operation transferring to a fast, zerowait-state memory target. The signals driven by the S5935 during the transfer are FRAME#, AD[31:0], C/ BE[3:0]#, and IRDY#. The signals driven by the target are DEVSEL# and TRDY#. As with PCI reads, targets assert DEVSEL# and TRDY# after the clock defining the end of the address phase (boundary of clock periods 1 and 2 of Figure 4). TRDY# is not driven until the target has accepted the data for the PCI write. When the S5935 becomes the PCI initiator, it attempts sus-
tained zero-wait state burst writes until one of the following occurs: * * * * * * The memory target aborts the transfer PCI bus grant (GNT# is removed) The Add-On to PCI FIFO becomes empty A higher priority (PCI to Add-On) S5935 transfer is pending (if programmed for priority) The write transfer byte count reaches zero Bus mastering is disabled from the Add-On interface
Write accesses to the S5935 operation registers (S5935 as a target) are shown in Figure 5. Here, the S5935 asserts the signal STOP# in clock period 3. STOP# is asserted because the S5935 supports fast, zero-wait-state write cycles but does not support burst writes to operation registers. Wait states may be added by the initiator by not asserting the signal IRDY# during clock 2 and beyond. There is only one condition where writes to S5935 operation registers do not return TRDY# (but do assert STOP#). This is called a target-initiated termination or target disconnect and occurs when a write attempt is made to a full S5935 FIFO. As with the read transfers, the assertion of STOP# without the assertion of TRDY# indicates the initiator should retry the operation later.
Figure 49. Zero Wait State Burst Write PCI Bus Transfer (S5935 as Initiator)
1 PCI CLOCK FRAME # AD [31:0] C/BE [3:0]# IRDY# TRDY# DEVSEL# (I)
ADDRESS BUS COMMAND* DATA 1 BYTE EN 1 DATA 2 BYTE EN 2 DATA 3 BYTE EN 3
2
3
45
6
(I) (I) (I) (T) (T)
* BUS COMMAND = MEMORY WRITE
DATA TRANSFER #1
DATA TRANSFER #2
DATA TRANSFER #3
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
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Master-Initiated Termination Normal Cycle Completion
Occasionally, a PCI transfer must be terminated by the initiator. Typically, the initiator terminates a transfer upon the successful completion of the transfer. Sometimes, the initiator's bus mastership is relinquished by the bus arbiter (GNT# is removed), often because another device requires bus ownership. This is called initiator preemption and is discussed in later Sections. When the S5935 is an initiator and does not observe a DEVSEL# response to its assertion of FRAME#, it terminates the cycle (master abort).
A successful data transfer occurs when both the initiator and target assert their respective ready signals, IRDY# and TRDY#. The last data phase is indicated by the initiator when FRAME# is deasserted during a data transfer. A normal cycle completion occurred if the target does not assert STOP#. Figure 6 shows the signal relationships defining a normal transfer completion.
Figure 50. Single Data Phase PCI Bus Write of S5935 Registers (S5935 as Target)
1 PCI CLOCK FRAME # AD [31:0] C/BE [3:0]# IRDY# TRDY# DEVSEL# STOP# (I)
ADDRESS BUS COMMAND DATA 1 BYTE EN 1
2
3
45
6
IF BURST ATTEMPT DATA 2 BYTE EN 2
(I) (I) (I) (T) (T) (T)
DATA TRANSFER #1
NO DATA TRANSFERRED
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
Figure 51. Master-Initiated, Normal Completion (S5935 as either Target or Initiator)
1 PCI CLOCK FRAME # IRDY# TRDY# (I) (I) (T) 2 3
DEVSEL# (T) STOP# (T)
NORMAL COMPLETION
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
PCI BUS INTERFACE S5935
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Initiator Preemption
A PCI initiator (bus master) is said to be preempted when the system platform deasserts the initiator's bus grant signal, GNT#, while it still requests the bus (REQ# asserted). This situation occurs if the initiator's latency timer expires and the system platform (bus arbitrator) has a bus master request from another device. The S5935 Master Latency Timer register controls the S5935 responsiveness to the removal of a bus grant (preemption). The presence of a Master
Latency Timer register can cause two preemption situations: 1. Removal of GNT# when the latency timer is nonzero (S5935 is guaranteed to still "own the bus"). 2. Removal of the GNT# after the latency timer has expired. The first situation is depicted in Figure 7, when the latency timer has not expired. Preemption with a zero or expired latency timer is shown in Figure 8.
Figure 52. Master Initiated Termination Due to Preemption and Latency Timer Active (S5935 as Master)
1 PCI CLOCK GNT # FRAME IRDY# TRDY# (I) (I) (T) 2 3 4 5 6
S5933 LATENCY =3 TIMER
=2
=1
=0
PREEMPTION
TIMEOUT SENSED
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
DATA TRANSFERRED
DATA TRANSFERRED
DATA TRANSFERRED
DATA TRANSFERRED
Figure 53. Master Initiated Termination Due to Preemption and Latency Timer Expired (S5935 as Master)
1 PCI CLOCK GNT # FRAME (I) IRDY# (I) 2 3 4 5
TRDY# (T)
S5933 =1 LATENCY TIMER
=0
PREEMPTION
DATA TRANSFERRED
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
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Master Abort
PCI accesses to nonexistent or disabled targets never observe DEVSEL# being asserted. In this situation, it is necessary for the initiator to abort the transaction (master abort). As an initiator, S5935 waits for six clock periods after asserting FRAME# to determine whether a master abort is required. These six clock periods allow slow targets, which may require several bus clocks before being able to assert DEVSEL#, to respond. It is also possible a PCI bridge device is present which employs "subtractive" decoding. A device which does a subtractive decode asserts DEVSEL#, claiming the cycle, when it sees that no other device has asserted it three clocks after the address phase.
Figure 54. Master Abort, No Response
1 PCI CLOCK FRAME # IRDY# TRDY# DEVSEL#
(I) (I) (T) (T)
If DEVSEL# is not asserted, the S5935 deasserts FRAME# (if asserted) upon the sixth clock period (Figure 9). IRDY# is deasserted by the S5935 during the next clock. The occurrence of a master abort causes the S5935 to set bit 13 (Master Abort) of the PCI Status Register, indicating an error condition.
Target-Initiated Termination
There are situations where the target may end a transfer prematurely. This is called "target-initiated termination." Target terminations fall into three categories: disconnect, retry, and target abort. Only the disconnect termination completes a data transfer.
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FAST DEVICE
MEDIUM DEVICE
SLOW DEVICE
BRIDGE DEVICE (SUBTRACTIVE DECODE)
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
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Target Disconnects
There are many situations where a target may disconnect. Slow responding targets may disconnect to permit more efficient (faster) devices to be accessed while they prepare for the next data phase, or a target may disconnect if it recognizes that the next data phase in a burst transfer is out of its address range. A target disconnects by asserting STOP#, TRDY#, and DEVSEL# as shown in Figures 10a and 10b. The initiator in Figure 10a responds to the disconnect condition by deasserting FRAME# on the following
clock but does not complete the data transfer until IRDY# is asserted. This situation can only occur when the S5935 is a target. When the S5935 is an initiator, IRDY# is always asserted during the data phase (no initiator wait states). The timing diagram in Figure 10b applies to the S5935 as either a target disconnecting or an initiator with its target performing a disconnect. The S5935 performs a target disconnect if a burst access is attempted to the PCI Operation Registers.
Figure 55. Target Disconnect Example 1 (IRDY# deasserted)
1 PCI CLOCK FRAME # IRDY# TRDY# STOP# DEVSEL# (I) (I) (T) (T) (T)
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
2
3
DATA TARGET DISCONNECT TRANSFERRED IDENTIFIED
Figure 10b. Target Disconnect Example 2 (IRDY# asserted)
1 PCI CLOCK FRAME # IRDY# TRDY# STOP# DEVSEL# (I) (I) (T) (T) (T) 2 3
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
DATA TARGET DISCONNECT TRANSFERRED SIGNALED, DATA TRANSFERRED
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Target Requested Retries Target Aborts
When the S5935 FIFO registers are accessed (S5935 as a target) and data is unavailable (empty FIFO) for read transfers or cannot be accepted for write transfers (full FIFO), the S5935 immediately terminates the cycle by requesting a retry. The S5935 also initiates a retry for Pass-Thru writes where the Add-On has not completed the preceding Pass-Thru write by asserting PTRDY#, and for Pass-Thru reads where the Add-On cannot supply data within 8 PCI clocks (16 clocks for the first data phase of a burst). A retry is requested by a target asserting both STOP# and DEVSEL# while TRDY# is deasserted. Figure 11 shows the behavior of the S5935 when performing a target-initiated retry.
Figure 56. Target-Initiated Retry
1 PCI CLOCK FRAME # IRDY# TRDY# STOP# DEVSEL# (I) (I) (T) (T) (T) 2
A target abort termination represents an error condition where no number of retries will produce a successful target access. A target abort is uniquely identified by the target deasserting DEVSEL# and TRDY# while STOP# is asserted. When a target performs an abort, it must also set bit 11 of its PCI Status register. The S5935 configuration and operation registers never respond with a target abort when accessed. If the S5935 encounters this condition when operating as a PCI initiator, the S5935 sets bit 12 (received target abort) in the PCI Status register. Figure 12 depicts a target abort cycle. Target termination types are summarized in Table 2.
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45
TARGET RETRY SIGNALED
INITIATOR SEQUENCES IRDY# + FRAME# TO RETURN TO IDLE STATE
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
Table 42. Target Termination Types
Termination Disconnect Retry Abort DEVSEL# on on off STOP# on on on TRDY# on off off Comment Data is transferred. Transaction needs to be reinitiated to complete. Data was not transferred. Transaction should be tried later. Data was not transferred. Fatal error.
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Figure 57. Target Abort Example
1 PCI CLOCK FRAME # IRDY# TRDY# STOP# DEVSEL# (I) (I) (T) (T) (T) 2 3
TARGET ABORT IDENTIFIED
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
Figure 58. PCI Bus Arbitration and S5935 Bus Ownership Example
1 2 34 56 7 89
S5933 REQ# "OTHER" REQ# S5933 GNT# "OTHER" GNT# FRAME# AD[31:0] IRDY# TRDY# IDLE S5933 TRANSACTION IDLE (TURNAROUND) "OTHER", PREEMPTING MASTER TRANSACTION S5933 TRANSACTION(S) ADDRESS DATA ADDRESS DATA ADDRESS DATA
IDLE (TURNAROUND)
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
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PCI BUS MASTERSHIP
When the S5935 requires PCI bus mastership, it presents a request via the REQ# signal. This signal is connected to the system's PCI bus arbiter. Only one initiator (bus master) may control the PCI bus at a given time. The bus arbiter determines which initiator is given control of the bus. Control is granted to a requesting device by the arbiter asserting that device's grant signal (GNT#). Each REQ#/ GNT# signal pair is unique to a given PCI agent. After asserting REQ#, the S5935 assumes bus ownership on the first PCI clock edge where its GNT# input is asserted along with FRAME# and IRDY# deasserted (indicating no other device is generating PCI bus cycles). Once ownership is established by the S5935, it maintains ownership as long as the arbiter keeps its GNT# asserted. If GNT# is deasserted, the S5935 completes the current transaction. The S5935 does this by deasserting FRAME# and then deasserting IRDY# upon data transfer. Figure 13 shows a sequence where the S5935 is granted ownership of the bus and then is preempted by another master before the S5935 can finish its current transaction.
Bus Mastership Latency Components
Once a PCI initiator has been granted the bus, the PCI specification defines the delay from the grant to the new initiator's assertion of FRAME# as the "bus acquisition latency." Afterwards, the delay from FRAME# asserted to target ready (TRDY#) asserted is defined as "target latency." Figure 14 shows a time-line depicting the components of PCI bus access latency. There are numerous configuration variations possible with the PCI specification. A system designer can determine whether a bus master can support a critical, timely transfer by establishing a specific configuration and by defining these latency values. The S5935, as an initiator, produces the fastest response allowable for its bus acquisition latency (GNT# to FRAME# asserted). The S5935 also implements the PCI Master Latency Timer. Once granted the bus, the S5935 is guaranteed ownership for a minimum amount of time defined by the Master Latency Timer. The S5935, as an initiator, cannot control the responsiveness of a particular target nor the bus arbitration delay. The PCI specification provides two mechanisms to control the amount of time a master may own the bus. One mechanism is through the master (master initiated termination). The other is by the target and is achieved through a target-initiated disconnect.
Bus Arbitration
It is often necessary for system designers to predict and guarantee that a minimum data transfer rate is sustainable to support a particular application. In the design of a bus mastering application, knowledge of the maximum delay a device might encounter from the time it requests the PCI bus to the time in which it is actually granted the bus is desirable. This allows the design to provide adequate data buffering. The PCI specification refers to this bus request to grant delay as "arbitration latency."
Figure 59. PCI Bus Access Latency Components
Although the PCI specification defines the condition that constitutes bus ownership, it does not provide rules to be used by the system's PCI bus arbiter in deciding which master is to be granted the PCI bus next. The arbitration priority scheme implemented by a system may be fixed, rotational, or custom. The arbitration latency is a function of the system, not the S5935.
Bus Access Latency
REQ# Asserted
GNT# Asserted --Bus Acquisition-Latency
FRAME# Asserted --Target Latency--
TRDY# Asserted
--Arbitration Latency--
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Bus Acquisition
Once GNT# is asserted, giving bus ownership to the S5935, the S5935 must wait until the PCI bus becomes idle. This delay is called bus acquisition latency and involves the state of the signals FRAME# and IRDY#. The current bus master must complete its current transaction before the S5935 may drive the bus. Table 3 depicts the four possible combinations of FRAME# and IRDY# with their interpretation.
Target Latency
potentially monopolizing the PCI bus and also allows more accurate estimations for bus access latency.
Target Locking
The PCI specification requires that a selected target relinquish the bus should an access to that target require more than eight PCI clock periods (16 clocks for the first data phase in a burst). Slow targets can exist within the PCI specification by using the target initiated retry. This prevents slow target devices from
It is possible for a PCI bus master to obtain exclusive access to a target ("locking") through use of the PCI bus signal LOCK#. LOCK# is different from the other PCI bus signals because its ownership may belong to any bus master, even if it does not currently have ownership of the PCI bus. The ownership of LOCK#, if not already claimed by another master, may be achieved by the current PCI bus master on the clock period following the initial assertion of FRAME#. Figure 15 describes the signal relationship for establishing a lock. The ownership of LOCK#, once established, persists even while other bus masters control the bus. Ownership can only be relinquished by the master which originally established the lock.
Figure 60. Engaging the LOCK# Signal
1 PCI CLOCK FRAME # LOCK # (I) AD[31:0] IRDY# TRDY# DEVSEL# (I) (T) (T)
ADDRESS
2
3
45
6
(I)
STILL DRIVEN BY PREVIOUS OWNER (TARGET IS LOCKED)
(T)
DATA
LOCK MECHANISM AVAILABLE UPON FIRST ACCESS
TARGET BECOMES LOCKED BUS IDLE LOCK ESTABLISHED LOCK MAINTAINED
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
LOCK MECHANISM AVAILABLE
Table 43. Possible Combinations of FRAME# and IRDY#
FRAME# deasserted deasserted asserted asserted IRDY# deasserted asserted deasserted asserted Bus Idle The initiator is ready to complete the last data transfer of a transaction. An Initiator has a transaction in progress but is not able to complete the data transfer on this clock. An initiator has a transaction in progress and is able to complete a data transfer. Description
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Targets selected with LOCK# deasserted during the assertion of FRAME# (clock period 1 of Figure 15), which encounter the assertion of LOCK# during the following clock (clock period 2 of Figure 15) are thereafter considered "locked." A target, once locked, requires that subsequent accesses to it deassert LOCK# while FRAME# is asserted. Figure 16 show a subsequent access to a locked target by the master which locked it. Because LOCK# is owned by a single master, only that master is able to deassert it at the beginning of a transaction (allowing successful access to the locked target). A locked target can only be unlocked during the clock period following the last data transfer of a transaction when the LOCK# signal is deasserted.
Figure 61. Access to a Locked Target by its Owner
1 PCI CLOCK FRAME # LOCK # AD [31:0] IRDY# TRDY# DEVSEL# (I)
ADDRESS DATA DATA
An unlocked target ignores LOCK# when it observes that LOCK# is already asserted during the first clock period of a transaction. This allows other masters to access other (unlocked) targets. If an access to a locked target is attempted by a master other than the one that locked it, the target responds with a retry request, as shown in Figure 17. The S5935 responds to and supports bus masters which lock it as a target. When the S5935 is a bus master, it never attempts to lock a target, but it honors a target's request for retry if that target is locked by another master.
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3
45
(I)
(I) (T) (T) LOCKED TARGET IDENTIFIES OWNER CONDITION WHICH UNLOCKS TARGET
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
Figure 62. Access Attempt to a Locked Target
1 PCI CLOCK FRAME # LOCK # AD [31:0] IRDY# TRDY# DEVSEL# STOP# (I)
ADDRESS DATA
2
3
45
(I)
(I) (T) (T) (T) LOCKED TARGET IDENTIFIES THAT BUS MASTER IS NOT ITS OWNER
CAUSES TARGET RETRY TERMINATION
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
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PCI BUS INTERRUPTS
The S5935 controller is able to generate PCI bus interrupts by asserting the PCI bus interrupt signal (INTA#). INTA# is a multisourced, wire-ORed signal on the PCI bus and is driven by an open drain output on the S5935. The assertion and deassertion of INTA# have no fixed timing relationship with respect to the PCI bus clock. Once the S5935 asserts INTA#, it remains asserted until the interrupt source is cleared by a write to the Interrupt Control/Status Register (INTCSR). phase, the SERR# signal is an open drain multisourced, wire-ORed signal on the PCI bus. The S5935 drives SERR# low for one clock period when an address phase error is detected. Once an SERR error is detected by the S5935, the PCI Status register bit 14, System Error, is set and remains until cleared through software or a hardware reset. The PERR# signal is similar to the SERR# with two differences: it reports errors for the data phase and is only asserted by the device receiving the data. The S5935 drives this signal (removed from tri-state) when it is the selected target for write transactions or when it is the current master for bus read transactions. The parity error conditions are only reflected by the PERR# pin if the Parity Error Enable bit (bit 6) of the PCI Command register is set. Upon the detection of a data parity error, the Detected Parity Error bit (bit 15) of the PCI Status Register is set. Unlike the PERR# signal pin, this Status bit sets regardless of the state of the PCI Command register Parity Error Enable bit. An additional status bit (bit 8) called "Data Parity Reported" of the PCI Status register is employed to report parity errors that occur when the S5935 is the bus master. The "Data Parity Error Reported" status requires that the Parity Error Enable bit be set in the PCI Command register. The assertion of PERR# occurs two clock periods following the data transfer. This two-clock delay occurs because the PAR signal does not become valid until the clock following the transfer, and an additional clock is provided to generate and assert PERR# once an error is detected. PERR# is only asserted for one clock cycle for each error sensed. The S5935 only qualifies the parity error detection during the actual data transfer portion of a data phase (when both IRDY# and TRDY# are asserted).
PCI BUS PARITY ERRORS
The PCI specification defines two error-reporting signals, PERR# and SERR#. These signals indicate a parity error condition on the signals AD[31:0], C/ BE[3:0]#, and PAR. The validity of the PAR signal is delayed one clock period from its corresponding AD[31:0] and C/BE[3:0]# signals. Even parity exists when the total number of ones in the group of signals is equal to an even number. PERR# is the errorreporting mechanism for parity errors that occur during the data phase for all but PCI Special Cycle commands. SERR# is the error-reporting mechanism for parity errors that occur during the address phase. The timing diagram in Figure 18 shows the timing relationships between the signals AD[31:0], C/BE[3:0]#, PAR, PERR# and SERR#. The S5935 asserts SERR# if it detects odd parity during an address phase, if enabled. The SERR# enable bit is bit 8 in the S5935 PCI Command Register. The odd parity error condition involves the state of signals AD[31:0] and C/BE[3:0]# when FRAME# is first asserted and the PAR signal during the following clock. If an error is detected, the S5935 asserts SERR# on the following (after PAR valid) clock. Since many targets may observe an error on an address
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Figure 63. Error Reporting Signals
12 PCI CLOCK FRAME AD[31:0] (I) C/BE[3:0]# PAR SERR# PERR# (T) (T)
A READ TRANSACTION
3
4
5
6
7
8
9
(I) (I) (T)
ADDR CMD A AA DATA A BYTE ENABLES
(I)
ADDR BB CMD BB
DATA BE's
(T)
GOOD A ERROR
(I)
GOOD B ERROR
GOOD A ERROR WRITE B TRANSACTION
GOOD B ERROR
(I) = DRIVEN BY INITIATOR (T) = DRIVEN BY TARGET
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ADD-ON BUS INTERFACE
This chapter describes the Add-On bus interface for the S5935. The S5935 is designed to support connection to a variety of microprocessor buses and/or peripheral devices. The Add-On interface controls S5935 operation through the Add-On Operation Registers. These registers act as the Pass-Thru, FIFO, non-volatile memory and mailbox interfaces as well as offering control and status information. Depending on the register being accessed, the interface may be synchronous or asynchronous. To enhance performance and simplify Add-On logic design, some registers allow direct access with a single device input pin. The following sections describe the various interfaces to the PCI bus and how they are accessed from the Add-On interface. chapters. The interrupt output is deasserted when acknowledged by an access to the Add-On Interrupt Control/Status Register (AINT). All interrupt sources are cleared by writing a one to the corresponding interrupt bit. The MODE input on the Add-On interface configures the datapath width for the Add-On interface. MODE low indicates a 32-bit data bus. MODE high indicates a 16-bit data bus. For 16-bit operation, BE3# is redefined as ADR1, providing an extra address input. ADR1 selects the low or high words of the 32-bit S5935 Add-On Operation Registers.
Register Access Signals
ADD-ON OPERATION REGISTER ACCESSES
The S5935 Add-On bus interface is very similar to that of a memory or peripheral device found in a microprocessor-based system. A 32-bit data bus with individual read and write strobes, a chip enable and byte enables are provided. Other Add-On interface signals are provided to simplify Add-On logic design. Accesses to the S5935 registers are done primarily synchronously to BPCLK. For S5935 functions that are compatible with an Add-On microprocessor interface, it is helpful to allow an asynchronous interface, as the processor may not operate at the PCI bus clock frequency.
Add-On Interface Signals
Simple register accesses to the S5935 Add-On Operation Registers take two forms: synchronous to BPCLK and asynchronous. The following signals are required to complete a register access to the S5935.
BE[3:0]# Byte Enable Inputs. These S5935 inputs identify valid byte lanes during Add-On transactions. When MODE is set for 16-bit operation, BE2# is not defined and BE3# becomes ADR1. ADR[6:2] Address Inputs. These address pins identify the specific Add-On Operation Register being accessed. When configured for 16-bit operation (MODE=1), an additional input, ADR1 is available to allow the 32-bit operation registers to be accessed with two 16-bit cycles. RD# Read Strobe Input. WR# Write Strobe Input. SELECT# Chip Select Input. This input identifies a valid S5935 access. DQ[31:0] Bidirectional Data Bus. These I/O pins are the S5935 data bus. When configured for 16-bit operation, only DQ[15:0] are valid.
The Add-On interface provides a small number of system signals to allow the Add-On to monitor PCI bus activity, indicate status conditions (interrupts), and allow Add-On bus configuration. A standard bus interface is provided for Add-On Operation Register accesses.
System Signals
BPCLK and SYSRST# allow the Add-On interface to monitor the PCI bus status. BPCLK is a buffered version of the PCI clock. The PCI clock can operate from 0 MHz to 33 MHz. SYSRST# is a buffered version of the PCI reset signal, and may also be toggled by host application software through bit 24 of the Bus Master Control/Status Register (MCSR). IRQ# is the Add-On interrupt output. This signal is active low and can indicate a number of conditions. Add-On interrupts may be generated from the mailbox or FIFO interfaces. The exact conditions which generate an interrupt are discussed in the mailbox and FIFO
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In addition, there are dedicated signals for FIFO accesses (RDFIFO# and WRFIFO#) and Pass-Thru address accesses (PTADR#). These are discussed separately in the FIFO and Pass-Thru sections of this chapter. The internal interfaces of the S5935 allow Add-On Operation Registers to be accessed asynchronous to BPCLK (synchronous to the rising edge of the read or write strobe). The exception to this is the Add-On General Control/Status Register. This is due to the async nature of FIFO status bits changing as the PCI bus reads data. For Pass-Thru operations, the Pass-Thru Data Register accesses are synchronous to BPCLK to support burst transfers. The FIFO port is also accessed synchronous to BPCLK.
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Asynchronous Register Accesses
For many Add-On applications, Add-On logic does not operate at the PCI bus frequency. This is especially true for Add-Ons implementing a microprocessor, which may be operating at a lower (or higher) frequency. Figures 1 and 2 show asynchronous Add-On Operation Register accesses. Exact AC timings are detailed in the Electrical and AC Characteristics chapter (Chapter 13). For asynchronous reads (Figure 1), data is driven on the data bus when RD# is asserted. When RD# is not asserted, the DQ[31:0] outputs float. A valid address and valid byte enables must be presented before correct data is driven. RD# has both a minimum inactive time and a minimum active time for asynchronous accesses. For asynchronous writes (Figure 2), data is clocked into the S5935 on the rising edge of the WR# input. Address, byte enables, and data must all meet setup and hold times relative to the rising edge or WR#. WR# has both a minimum inactive time and a minimum active time for asynchronous accesses.
Synchronous FIFO and Pass-Thru Data Register Accesses
For synchronous reads (Figure 3), data is driven onto the data bus when RD# (or RDFIFO#) is asserted. When RD# is not asserted, the DQ[31:0] outputs float. The address, byte enable, and RD# inputs must meet setup and hold times relative to the rising edge of BPCLK. Burst reads may be performed by holding RD# low. For synchronous writes (Figure 4), data is clocked into the register on the rising edge of BPCLK. Address, byte enables, and data must all meet setup and hold times relative to the rising edge or BPCLK. Burst writes may be performed by holding WR# (or WRFIFO#) low. When holding WR# low, data is clocked in on each BPCLK rising edge.
nv Memory Accesses Through the Add-On General Control/Status Register
To obtain the highest data transfer rates possible, AddOn logic should operate synchronously with the PCI clock. The buffered PCI clock (BPCLK) is provided for this purpose. A synchronous interface with Pass-Thru mode or the FIFO allows data to be transferred at the maximum PCI bus bandwidth (132 MBytes/sec) by allowing burst accesses with the Add-On interface. The RD# and WR# inputs become enables, using BPCLK to clock data into and out of registers. This section applies only to synchronous accesses to the FIFO (AFIFO) and Pass-Thru Data (APTD) registers. Figures 3 and 4 show single-cycle, synchronous FIFO and Pass-Thru Operation Register accesses. Exact AC timings are detailed in the Electrical and AC Characteristics chapter.
To access nv memory contents through the Add-On General Control/Status Register (AGCSTS), special considerations must be made. Internally, all nv memory accesses by the S5935 are synchronized to a divided-down version of the PCI bus clock. Because of this, if nv memory accesses are performed through the AGCSTS register, the register access must be synchronized to BPCLK. The rising edge RD# or WR# is still used to clock data, but these inputs along with the address and byte enables are synchronized to BPCLK. Accesses to AGCSTS for monitoring FIFO or mailbox status, etc., may be done asynchronous to BPCLK.
MAILBOX BUS INTERFACE
The mailbox register names may need some clarification. For the Add-On interface, an outgoing mailbox refers to a mailbox sending information to the PCI bus. An incoming mailbox refers to a mailbox receiving information from the PCI bus. An outgoing mailbox on the Add-On interface is, internally, the same as the corresponding incoming mailbox on the PCI interface and vice-versa.
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Figure 64. Asynchronous Add-On Operation Register Read
BE[3:0]#
Valid Byte Enables
ADR[6:2]
Valid Address
DQ[31:0]
Valid Data Out
SELECT# RD#
Figure 65. Asynchronous Add-On Operation Register Write
BE[3:0]#
Valid Byte Enables
ADR[6:2]
Valid Address
DQ[31:0]
Valid Data In
SELECT# WR#
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Figure 66. Synchronous FIFO or Pass-Thru Data Register Read
BPCLK ADR[6:2] BE[3:0]# DQ[31:0] RD# RDFIFO# SELECT#
Valid 1
Valid 2
Valid Data Out 1
Valid Data Out 2
Figure 67. Synchronous FIFO or Pass-Thru Data Register Write
BPCLK ADR[6:2] BE[3:0]# DQ[31:0] WR# WRFIFO# SELECT#
Valid 1
Valid 2
Valid Data In 1
Valid Data In 2
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Mailbox Interrupts
Mailboxes can be configured to generate Add-On interrupts (IRQ#) and/or allow the Add-On to generate PCI interrupts (INTA#). Mailbox empty/full status conditions be can used to interrupt the Add-On or PCI host to indicate some action is required. An individual mailbox byte is selected to generate an interrupt when accessed. An outgoing mailbox becoming empty or an incoming mailbox becoming full asserts the interrupt output (if enabled). When used with a serial nv memory boot device, the mailboxes also provide a way to generate PCI interrupts (INTA#) through hardware. When a serial nv memory boot device is used, the device pin functions EA0 - EA8 are redefined. These pins then provide direct, external access to the Add-On outgoing mailbox 4, byte 3 (which is also PCI incoming mailbox 4, byte 3).
a short propagation delay) after the access occurs. For Add-On accesses, FIFO status is updated after the rising edge of BPCLK for synchronous interfaces or after the rising edge of the read or write strobe for asynchronous interfaces.
FIFO Control Signals
For Add-On initiated PCI bus mastering, the FIFO status reset controls FWC# (Add-On to PCI FIFO clear) and FRC# (PCI to Add-On FIFO clear) are available. FWC# and FRC# must be asserted for a minimum of one BPCLK period to be recognized. These inputs are sampled at the rising edge of BPCLK. These inputs should not be asserted unless the FIFO is idle. Asserting a FIFO status reset input during a PCI or Add-On FIFO access results in indeterminate operation. For Add-On initiated bus master transfers, AMREN (Add-On bus master read enable) and AMWEN (AddOn bus master write enable) are used, in conjunction with the appropriate FIFO status signals, to enable the S5935 to assert its PCI bus request (REQ#).
FIFO BUS INTERFACE
The FIFO register on the Add-On interface may only be accessed synchronously or asynchronously. Location 45h, bits 6 and 5 in the nv memory boot device must be programmed to a "0" for correct operation.
FIFO Direct Access Inputs
PASS-THRU BUS INTERFACE
The S5935 Pass-Thru interface is synchronous. The Add-On Pass-Thru Address (APTA) and Add-On Pass-Thru Data (APTD) registers may be accessed pseudo-synchronously. Although BPCLK is used to clock data into and out of the Pass-Thru registers, accesses may be performed asynchronously. For reads, APTA or APTD data remains valid as long as RD# (or PTADR#) is asserted. A new value is not driven until PTRDY# is asserted by Add-On logic. For writes to APTD, data is clocked into the S5935 on every BPCLK rising edge, but is not passed to the PCI bus until PTRDY# is asserted. PTRDY# must by synchronized to BPCLK.
Pass-Thru Status Indicators
RDFIFO# and WRFIFO# are referred to as FIFO `direct access' inputs. Asserting RDFIFO# is functionally identical to accessing the FIFO with RD#, SELECT#, BE[3:0]#, and ADR[6:2]. Asserting WRFIFO# is functionally identical to accessing the FIFO with WR#, SELECT#, BE[3:0]#, and ADR[6:2]. RD# and WR# must be deasserted when RDFIFO# or WRFIFO# is asserted, but SELECT# may be asserted. These inputs automatically drive the address (internally) to 20h and assert all byte enables. The ADR[6:2] and BE[3:0]# inputs are ignored when using the FIFO direct access inputs. RDF IF O# and WRFIFO# are useful for Add-On designs which cascade an external FIFO into the S5935 FIFO or use dedicated external logic to access the FIFO. Direct access signals always access the FIFO as 16bits or 32-bits, whatever the MODE pin is configured for. For 16-bit mode, two consecutive accesses fill or empty the 32-bit FIFO register.
FIFO Status Signals
The Pass-Thru status indicators indicate that a PassThru access is in process and what action is required by the Add-On logic to complete the access. All PassThru status indicators are synchronous with the PCI clock.
Pass-Thru Control Inputs
The FIFO Status signals indicate to the Add-On logic the current state of the S5935 FIFO. A FIFO status change caused by a PCI FIFO access is reflected one PCI clock period after the PCI access is completed (TRDY# asserted). A FIFO status change caused by an Add-On FIFO access is reflected immediately (after
Some Pass-Thru implementations may require an address corresponding to the Pass-Thru data. The Add-On Pass-Thru Address Register (APTA) contains the PCI address for the Pass-Thru cycle. To allow access to the Pass-Thru address without generating an Add-On read cycle, PTADR# is provided. PTADR# is a direct access input for the Pass-Thru address. Asserting PTADR# is functionally identical to accessing the Pass-Thru address register with RD#,
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SELECT#, BE[3:0]#, and ADR[6:2]. RD# and WR# must be deasserted when PTADR# is asserted, but SELECT# may be asserted. These inputs automatically drive the address (internally) to 28h and assert all byte enables. The ADR[6:2] and BE[3:0]# are ignored when using the PTADR# direct access input. When PTADR# is asserted, the contents of the APTA register are immediately driven onto the Add-On data bus. The PTADR# direct access signal accesses the PassThru address register as 16-bits or 32-bits, whatever the MODE pin is configured for. For 16-bit mode, PTADR# only presents the lower 16-bits of the APTA register. PTRDY# indicates that the Add-On has completed the current Pass-Thru access. Multiple Add-On reads or writes may occur to the Pass-Thru data (APTD) register before asserting PTRDY#. This may be required for 8-bit or 16-bit Add-On interfaces using multiple accesses to the 32-bit Pass-Thru data register. In some cases, the Add-On bus may be 32-bits, but logic may require multiple BPCLK periods to read or write data. In this situation, accesses may be extended by holding off PTRDY#. PTRDY# must be synchronized to BPCLK. The S5935 automatically performs the read and write accesses when programmed for byte wide devices.
Accessing Non-Volatile Memory
The nv memory, if implemented, can be accessed through the PCI interface or the Add-On interface. Accesses from both the PCI side and the Add-On side must be synchronous with the PCI clock (BPCLK for the Add-On). Accesses to the nv memory from the PCI interface are through the Bus Master Control/Status Register (MCSR) PCI Operation Register. Accesses to the nv memory from the Add-On interface are through the Add-On General Control/Status Register (AGCSTS) Add-On Operation Register. Accesses to the MCSR register are from the PCI bus and are, therefore, automatically synchronous to the PCI clock. Accesses to the AGCSTS register from the Add-On side must be synchronous with respect to BPCLK. Some nv memories may contain Expansion ROM BIOS code for use by the host software. During initialization, the Expansion BIOS is located within system memory. The starting location of the nv memory is stored in the Expansion ROM Base Address Register in the S5935 PCI Configuration Registers. A PCI read from this region results in the S5935 performing four consecutive byte access to the nv memory device. Writes to the nv memory are not allowed by writing to this region. Writes to the nv memory must be performed as described below. The S5935 contains two latches within the MCSR register to control and access the NVRAM. One is an 8 bit latch called the NVRAM Address/Data Register which is used to hold NVRAM address and data information. The other is a 3 bit latch called the NVRAM Access Control Register which is used to direct the address and data information and to control the NVRAM itself. Reading or writing to the NVRAM is performed through bits D31:29 of this register. These bits are enable and decode controls rather than a command or instruction to be executed. D31 of this register is the primary enable bit which allows all accesses to occur. When written to a `1', D31 enables the decode bits D30 and D29 to direct the data contained in the address/data latch, D23:16, to the low address, high address or data latches. D31 should be thought of as "opening a door" where as long as D31 = 1, then the door is open for address or data information to be altered. The table on page 5-16 of the S5935 data book shows the D31:29 bit combinations for reading, writing, and loading address/data information. Additionally, D31 doubles as an S5935 status bit. A `1' indicates that the S5935 is currently busy reading or writing to the NVRAM. A `0' indicates a complete or inactive state.
NON-VOLATILE MEMORY INTERFACE
The S5935 allows read and write access to the nv memory device used for configuration. Reads are necessary during device initialization as configuration information is downloaded into the S5935. If an expansion BIOS is implemented in the nv memory, the host transfers (shadows) the code into system DRAM. Writes are useful for in-field updates to expansion BIOS code. This allows software to update the nv memory contents without altering hardware.
Non-Volatile Memory Interface Signals
For serial nv memory devices, there are only two signals used to interface with nv memory. SCL is the serial clock, and SDA is the serial data line. The functionality of these signals is described in-detail in the PIN description Section of this book. The designer does not need to generate the timings for SCL and SDA. The S5935 automatically performs the correct serial access when programmed for serial devices. For byte-wide nv memory devices, there is an 8-bit data bus (EQ7:0), and a 16-bit address bus (EA15:0) dedicated for the nv memory interface. When a serial nv memory is implemented, many of these pins have alternate functions. The S5935 also has read (ERD#) and write (EWR#) outputs to drive the OE# and WR# inputs on a byte-wide nv memory. The designer does not need to generate the timings for these outputs.
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For the examples below, we will assume the S5935 is I/O mapped with a base address of FC00h. These examples will read one byte of the Vendor ID and write one byte to the Vendor ID.
This example will write 1 byte from NVRAM location 0040h and read it back: In Out Out Out Out Out Out Out In Out In In FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). FC00h + 3FH an 80h (CMD to load the low address byte). This sets decode bits and opens door for low address latch. FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the decode bits and opens the door for the high address latch. FC00h + 3Eh a 00h (the high byte of the address desired). 00h goes into the latch but is not latched yet. FC00h + 3Fh an 00h (inactive CMD). This latches the high address through the disabling D31, `closes the door'. FC00h + 3Eh DATA (the data byte to be written). DATA byte goes into the latch but is not latched yet. FC00h + 3Fh a C0h (CMD to write the data byte). This latches the data byte through changing the decode bits and begins to write NVRAM data operation. FC00h + 3Fh until D31 = 0 (not busy). FC00h + 3Fh an E0h (CMD to read the address latched). FC00h + 3Fh until D31 = 0 (not busy). FC00h + 3Eh the data.
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This example will read 1 byte from NVRAM location 0040h: In Out Out Out Out Out In In FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). FC00h + 3Fh an 80h (CMD to load the low address byte). This sets decode bits and opens door for low address latch. FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the decode bits and opens the door for the high address latch. FC00h + 3Eh a 00h (the high byte of the address desired) 00h goes into latch but is not latched yet. FC00h + 3Fh an E0h (CMD to read NVRAM data). This latches the high address through changing the decode bits and begins to read the NVRAM data operation. FC00h + 3Fh until D31 = 0 (not busy). FC00h + 3Eh the data.
This example will read 1 byte from NVRAM location 0041h and contains an extra step to demonstrate D31 operation: In Out Out Out Out Out Out In In
Notes: 1. Latched addresses do not automatically increment after a read or write. They must be loaded with new values. 2. Latched addresses remain after reads and writes. It is allowable to only update one address byte for the next access. 3. A processor may perform a one word write to load an address byte and control command simultaneously.
FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). FC00h + 3Fh an 80h (CMD to load the low address byte). This sets decode bits and opens the door for low address latch. FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. FC00h + 3Eh (offset of Address/Data Register) 41h (the low byte of the address desired) 41h goes into latch but is not latched yet. FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the decode bits and opens the door for the high address latch. FC00h + 3Eh 00h (the high byte of the address desired) 00h goes into latch but is not latched yet. FC00h + 3Fh an E0h (CMD to read the address latched). This latches the high address through changing the decode bits and begins the read NVRAM data operation. FC00h + 3Fh until D31 = 0 (not busy). FC00h + 3Eh the data.
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nv Memory Device Timing Requirements Memory Device Requirements for Read Accesses
Timing Read cycle time Address valid to data valid Address valid to read active Read active to data valid Read pulse width Data hold from read inactive Spec. 8T(max) 7T-10(max) T(max) 6T-10(max) 6T(max) -- T = 30 ns 240 ns 200 ns 30 ns 170 ns 180 ns 2 ns
For serial nv memory devices, the serial clock output frequency is the PCI clock frequency divided by 512. This is approximately 65 KHz (with a 33 MHz PCI clock). Any serial memory device that operates at this frequency is compatible with the S5935. For byte-wide accesses, the S5935 generates the waveforms shown in Figures 5 and 6. Figure 5 shows an nv memory read operation. Figure 6 shows an nv memory write operation. Read operations are always the same length. Write operations, due to the characteristics of reprogrammable nv memory devices, may be controlled through a programming sequence.
Figure 68. nv Memory Read Operation
t35
ERD#
(OUTPUT)
t37 t38 t36
Address Valid
t39
EA[15:0]
(OUTPUT)
t40
EQ[7:0]
(INPUT)
t41
Data Valid
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Memory Device Requirements for Write Accesses
Timing Write cycle time Address valid to write active Data valid to write inactive Data hold from write inactive Write pulse width Write inactive Spec. 8T T(max) 6T+10(max) T(max) 6T(max) Note 2 T = 30 ns Note 1 30 ns 190 ns 30 ns 180 ns 2 ns
Figure 69. nv Memory Write Operation
t42 t43
EWR#
(OUTPUT)
t44 t39
Address Valid
t38
EA[15:0]
(OUTPUT)
t45
EQ[7:0]
(OUTPUT)
t46
Data Valid
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MAILBOX OVERVIEW
The S5935 has eight 32-bit mailbox registers. The mailboxes are useful for passing command and status information between the Add-On and the PCI bus. The PCI interface has four incoming mailboxes (Add-On to PCI) and four outgoing mailboxes (PCI to Add-On). The Add-On interface has four incoming mailboxes (PCI to Add-On) and four outgoing mailboxes (Add-On to PCI). The PCI incoming and Add-On outgoing mailboxes are the same, internally. The Add-On incoming and PCI outgoing mailboxes are also the same, internally. The mailbox status may be monitored in two ways. The PCI and Add-On interfaces each have a mailbox status register to indicate the empty/full status of bytes within the mailboxes. The mailboxes may also be configured to generate interrupts to the PCI and/or AddFigure 70. Block Diagram - PCI to Add-On Mailbox Register
MAILBOX REGISTER PCI BUS "OUTGOING MAILBOX" ADD-ON BUS "INCOMING MAILBOX" SELECT OUTPUT INTERLOCK LATCH OUTPUT DRIVER ADD-ON BUS "INCOMING MAILBOX"
On interface. One outgoing and one incoming mailbox on each interface can be configured to generate interrupts.
FUNCTIONAL DESCRIPTION
Figure 1 shows a block diagram of the PCI to Add-On mailbox registers. Add-On incoming mailbox read accesses pass through an output interlock latch. This prevents a PCI bus write to a PCI outgoing mailbox from corrupting data being read by the Add-On. Figure 2 shows a block diagram of the Add-On to PCI mailbox registers. PCI incoming mailbox reads also pass through an interlocking mechanism. This prevents an Add-On write to an outgoing mailbox from corrupting data being read by the PCI bus. The following sections describe the mailbox flag functionality and the mailbox interrupt capabilities.
PCI BUS INTERFACE
D
Q
D
Q
LOAD ENABLE
EN
EN ADD-ON RD# SELECT#
READ ENABLE S D Q MAILBOX FULL
"O"
EMPTY/FULL FF SELECTED READ ENABLE
Figure 71. Block Diagram - Add-On to PCI Mailbox Register
PCI BUS "INCOMING MAILBOX" OUTPUT INTERLOCK LATCH PCI "INCOMING MAILBOX" SELECT MAILBOX REGISTER ADD-ON BUS "OUTGOING MAILBOX"
PCI BUS INTERFACE
QD
QD
EN PCI READ PULSE ADD-ON WRITE PULSE WR# SELECT#
MAILBOX FULL
S Q D "O" REGISTER DECODE OF ADR[6:2] BE[3:0]#
EMPTY/FULL FF SELECTED READ PULSE
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Mailbox Empty/Full Conditions
The PCI and Add-On interfaces each have a mailbox status register. The PCI Mailbox Empty/Full Status (MBEF) and Add-On Mailbox Empty/Full Status (AMBEF) Registers indicate the status of all bytes within the mailbox registers. A write to an outgoing mailbox sets the status bits for that mailbox. The byte enables determine which bytes within the mailbox become full (and which status bits are set). An outgoing mailbox for one interface is an incoming mailbox for the other. Therefore, incoming mailbox stat u s b i ts o n o n e i n t e r f a c e a r e i d e n t i c a l t o t h e corresponding outgoing mailbox status bits on the other interface. The following list shows the relationship between the mailbox registers on the PCI and Add-On interfaces.
PCI Interface Outgoing Mailbox1 Outgoing Mailbox 2 Outgoing Mailbox 3 Outgoing Mailbox 4 Incoming Mailbox 1 Incoming Mailbox 2 Incoming Mailbox 3 Incoming Mailbox 4 PCI Mailbox Empty/Full = = = = = = = = = Add-On Interface Incoming Mailbox 1 Incoming Mailbox 2 Incoming Mailbox 3 Incoming Mailbox 4 Outgoing Mailbox 1 Outgoing Mailbox 2 Outgoing Mailbox 3 Outgoing Mailbox 4 Add-On Mailbox Empty/ Full
To reset individual flags in the MBEF and AMBEF registers, the corresponding byte must be read from the incoming mailbox. The PCI and Add-On mailbox status registers, MBEF and AMBEF, are read-only. Mailbox flags may be globally reset from either the PCI interface or the Add-On interface. The PCI Bus Master Control/Status Register (MCSR) and the Add-On General Control/Status Register (AGCSTS) each have a bit to reset all of the mailbox status flags.
Mailbox Interrupts
The designer has the option to generate interrupts to the PCI and Add-On interfaces when specific mailbox events occur. The PCI and Add-On interfaces can each define two conditions where interrupts may be generated. An interrupt can be generated when an incoming mailbox becomes full and/or when an outgoing mailbox becomes empty. A specific byte within a specific mailbox is selected to generate the interrupt. The conditions defined to generate interrupts to the PCI interface do not have to be the same as the conditions defined for the Add-On interface. Interrupts are cleared through software. For incoming mailbox interrupts, when the specified byte becomes full, an interrupt is generated. The interrupt might be used to indicate command or status information has been provided, and must be read. For PCI incoming mailbox interrupts, the S5935 asserts the PCI interrupt, INTA#. For Add-On incoming mailbox interrupts, the S5935 asserts the Add-On interrupt, IRQ#. For outgoing mailbox interrupts, when the specified byte becomes empty, an interrupt is generated. The interrupt might be used to indicate that the other interface has received the last information sent and more may be written. For PCI outgoing mailbox interrupts, the S5935 asserts the PCI interrupt, INTA#. For AddOn outgoing mailbox interrupts, the S5935 asserts the Add-On interrupt, IRQ#.
Add-On Outgoing Mailbox 4, Byte 3 Access
A write to an outgoing mailbox also writes data into the incoming mailbox on the other interface. It also sets the status bits for the outgoing mailbox and the status bits for the incoming mailbox on the other interface. Reading the incoming mailbox clears all corresponding status bits in the Add-On and PCI mailbox status registers (AMBEF and MBEF). For example, a PCI write is performed to the PCI outgoing mailbox 2, writing bytes 0 and 1 (BE0# and BE1# asserted). Reading the PCI Mailbox Empty/Full Status Register (MBEF) indicates that bits 4 and 5 are set. These bits indicate that outgoing mailbox 2, bytes 0 and 1 are full. Reading the Add-On Mailbox Empty/ Full Status Register (AMBEF) shows that bits 4 and 5 in this register are also set, indicating Add-On incoming mailbox 2, bytes 0 and 1 are full. An Add-On read of incoming mailbox 2, bytes 0 and 1 clears the status bits in both the MBEF and AMBEF status registers.
PCI incoming mailbox 4, byte 3 (Add-On outgoing mailbox 4, byte 3) does not function exactly like the other mailbox bytes. When an a serial nv memory boot device or no external boot device is used, the S5935 pins EA7:0 are redefined to provide direct external access to Add-On outgoing mailbox 4, byte 3. EA8 is redefined to provide a load clock which may be used
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to generate a PCI interrupt. The pins are redefined as follows: PCI incoming and outgoing mailbox interrupts are enabled in the Interrupt Control/Status Register (INTCSR). The mailboxes can generate a PCI interrupt (INTA#) under two conditions (individually enabled). For an incoming mailbox full interrupt, INTA# is asserted on the PCI clock rising edge after the AddOn mailbox write completes. For an outgoing mailbox empty interrupt, INTA# is asserted on the PCI clock rising edge after the Add-On mailbox read completes (the rising edge of RD#). INTA# is deasserted on the next PCI clock rising edge after the PCI access to clear the mailbox interrupt completes (TRDY# deasserted).
Add-On Bus Interface
Signal Pin EA0/EMB0 EA1/EMB1 EA2/EMB2 EA3/EMB3 EA4/EMB4 EA5/EMB5 EA6/EMB6 EA7/EMB7 EA8/EMBCLK
Add-On Outgoing Mailbox Mailbox 4, bit 24 Mailbox 4, bit 25 Mailbox 4, bit 26 Mailbox 4, bit 27 Mailbox 4, bit 28 Mailbox 4, bit 29 Mailbox 4, bit 30 Mailbox 4, bit 31 Mailbox 4, byte 3 load clock
If the S5935 is programmed to generate a PCI interrupt (INTA#), on an Add-On write to outgoing mailbox 4, byte 3, a rising edge on EMBCLK generates a PCI interrupt. The bits EMB7:0 can be read by the PCI bus interface by reading the PCI incoming mailbox 4, byte 3. These bits are useful to indicate various conditions which may have caused the interrupt. When using the S5935 with a byte-wide boot device, the capability to generate PCI interrupts with Add-On hardware does not exist. In this configuration, PCI incoming mailbox 4, byte 3 (Add-On incoming mailbox 4, byte 3) cannot be used to transfer data from the Add-On - it always returns zeros when read from the PCI bus. This mailbox byte is sacrificed to allow the added functionality provided when a byte-wide boot device is not used.
The Add-On mailbox interface behaves similar to the PCI bus interface. Add-On writes to full outgoing mailboxes overwrite data currently in that mailbox. PCI reads from empty incoming mailboxes return the data that was previously contained in the mailbox. Add-On incoming and outgoing mailbox interrupts are enabled in the Add-On Interrupt Control/Status Register (AINT). The mailboxes can generate the Add-On IRQ# interrupt under two conditions (individually enabled). For an incoming mailbox full interrupt, IRQ# is asserted one PCI clock period after the PCI mailbox write completes (TRDY# deasserted). For an outgoing mailbox empty interrupt, IRQ# is asserted one PCI clock period after the PCI mailbox read completes (TRDY# deasserted). IRQ# is deasserted immediately when the Add-On clears the mailbox interrupt. When the S5935 is used with a serial nv memory boot device or no external boot device, the device pins EA8:0 are redefined. EA7:0 become EMB7:0 data inputs and EA8 becomes EMBCLK, a load clock. This configuration allows the Add-On to generate PCI interrupts with a low-to-high transition on EMBCLK. The PCI incoming mailbox interrupt must be enabled and set for mailbox 4, byte3 in the PCI Interrupt Control/ Status Register (INTCSR). EMBCLK should begin high and be pulsed low, then high to be recognized. The rising edge of EMBCLK generates the interrupt. The rising edge of EMBCLK also latches in the values on EMB7:0. The S5935 interrupt logic must be cleared (INTA# deasserted) through INTCSR before further EMBCLK interrupts are recognized.
8-Bit and 16-Bit Add-On Interfaces
BUS INTERFACE
The mailboxes appear on the Add-On and PCI bus interfaces as eight operation registers. Four are outgoing mailboxes, four are incoming mailboxes. The mailboxes may be used to generate interrupts to each of the interfaces. The following sections describe the Add-On and PCI bus interfaces for the mailbox registers.
PCI Bus Interface
The mailboxes are only accessible with the S5935 as a PCI target. The mailbox operation registers do not support burst accesses by an initiator. A PCI initiator attempting to burst to the mailbox registers causes the S5935 to respond with a target disconnect with data. PCI writes to full outgoing mailboxes overwrite data currently in that the mailbox. PCI reads from empty incoming mailboxes return the data that was previously contained in the mailbox. Neither of these situations cause a target retry or abort.
Some Add-On designs may implement an 8-bit or 16bit bus interface. The mailboxes do not require a 32-bit Add-On interface. For 8-bit interfaces, the 8-bit data bus may be externally connected to all four bytes of the 32-bit Add-On interface (DQ 31:24, 23:16, 15:8, 7:0 are all connected). The Add-On device reading or
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writing the mailbox registers may access all mailbox bytes by cycling through the Add-On byte enable inputs. A similar solution applies to 16-bit Add-On buses. This solution works for Add-Ons which always use just 8-bit or just 16-bit accesses. If the MODE pin is high, indicating a 16-bit Add-On interface, the previous solution may be modified for an 8-bit interface. The difference is that ADR1 must be toggled after the first two accesses to steer the S5935 internal data bus to the upper 16-bits of the mailboxes.
Mailbox Status
Every byte in each mailbox has a status bit in the Mailbox Empty/Full Status Registers (MBEF and AMBEF). Writing a particular byte into an outgoing mailbox sets the corresponding status bit in both the MBEF and AMBEF registers. A read of a `full' byte in a mailbox clears the status bit. The MBEF and AMBEF are readonly. Status bits cannot cleared by writes to the status registers. The S5935 allows the mailbox status bits to be reset through software. The Bus Master Control/Status (MCSR) PCI Operation Register and the Add-On General Control/Status (AGCSTS) Add-On Operation Register each have a bit to reset mailbox status. Writing a `1' to Mailbox Flag Reset bit in the MCSR or the AGCSTS register immediately clears all bits in the both the MBEF and AMBEF registers. Writing a `0' has no effect. The Mailbox Flag Reset bit is write-only. The flag bits should be monitored when transferring data through the mailboxes. Checking the mailbox status before performing an operation prevents data from being lost or corrupted. The following sequences are suggested for PCI mailbox operations using status polling (interrupts disabled):
CONFIGURATION
The PCI interface and the Add-On interface each have four incoming mailboxes (IMBx or AIBMx) and four outgoing mailboxes (OMBx or AOMBx) along with a single mailbox status register (MBEF or AMBEF). Outgoing mailboxes are read/write, incoming mailboxes and the mailbox status registers are read-only. The following sections discuss the registers associated with the mailboxes and accesses required for different modes of mailbox operation.
Reading a PCI Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the AddOn interface. MBEF Bits 31:16 If a bit is set, valid data is contained in the corresponding mailbox byte.
2. Read Mailbox(es). Read the mailbox bytes which MBEF indicates are full. This automatically resets the status bits in the MBEF and AMBEF registers. IMBx Bits 31:0 Mailbox data.
Writing a PCI Outgoing Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the mailbox has been read by the Add-On interface. Writes to full mailbox bytes overwrite data currently in the mailbox (if not already read by the Add-On interface). Repeat until the byte(s) to be written are empty. MBEF Bits 15:0 If a bit is set, valid data is contained in the corresponding mailbox byte and has not been read by the Add-On.
2. Write Mailbox(es). Write to the outgoing mailbox byte(s). OMBx Bits 31:0 Mailbox data.
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Mailbox operations for the Add-On interface are functionally identical. The following sequences are suggested for Add-On mailbox operations using status polling (interrupts disabled):
Reading an Add-On Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the PCI interface. AMBEF Bits 15:0 If a bit is set, valid data is contained in the corresponding mailbox byte.
2. Read Mailbox(es). Read the mailbox bytes which AMBEF indicates are full. This automatically resets the status bits in the AMBEF and MBEF registers. AIMBx Bits 31:0 Mailbox data.
Writing an Add-On Outgoing Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the mailbox has been read by the PCI interface. Writes to full mailbox bytes overwrite data currently in the mailbox (if not already read by the PCI interface). Repeat until the byte(s) to be written are empty. AMBEF Bits 31:16 If a bit is set, valid data is contained in the corresponding mailbox byte and has not been read by the PCI bus.
2. Write Mailbox(es). Write to the outgoing mailbox byte(s). AOMBx Bits 31:0 Mailbox data.
Mailbox Interrupts
Although polling status is useful, in some cases, polling requires continuous actions by the processor reading or writing the mailbox. Mailbox interrupt capabilities are provided to avoid much of the processor overhead required by continuously polling status bits. The Add-On and PCI interface can each generate interrupts on an incoming mailbox condition and/or an outgoing mailbox condition. These can be individually enabled/disabled. A specific byte in one incoming mailbox and one outgoing mailbox is identified to generate the interrupt(s). The tasks required to setup mailbox interrupts are shown below:
Enabling PCI mailbox interrupts: 1. Enable PCI outgoing mailbox interrupts. A specific byte within one of the outgoing mailboxes is identified to assert INTA# when read by the Add-On interface. INTCSR INTCSR INTCSR Bit 4 Bits 3:2 Bits 1:0 Enable outgoing mailbox interrupts Identify mailbox to generate interrupt Identify mailbox byte to generate interrupt
2. Enable PCI incoming mailbox interrupts. A specific byte within one of the incoming mailboxes is identified to assert INTA# when written by the Add-On interface. INTCSR INTCSR INTCSR Bit 12 Bits 11:10 Bits 9:8 Enable incoming mailbox interrupts Identify mailbox to generate interrupt Identify mailbox byte to generate interrupt
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Enabling Add-On mailbox interrupts: 1. Enable Add-On outgoing mailbox interrupts. A specific byte within one of the outgoing mailboxes is identified to assert IRQ# when read by the PCI interface. AINT AINT AINT Bit 12 Bits 11:10 Bits 9:8 Enable outgoing mailbox interrupts Identify mailbox to generate interrupt Identify mailbox byte to generate interrupt
2. Enable Add-On incoming mailbox interrupts. A specific byte within one of the incoming mailboxes is identified to assert IRQ# when written by the PCI interface. AINT AINT AINT Bit 4 Bits 3:2 Bits 1:0 Enable incoming mailbox interrupts Identify mailbox to generate interrupt Identify mailbox byte to generate interrupt
With either the Add-On or PCI interface, these two steps can be performed with a single access to the appropriate register. They are shown separately here for clarity.
Once interrupts are enabled, the interrupt service routine must access the mailboxes and clear the interrupt source. A particular application may not require all of the steps shown. For instance, a design may only use incoming mailbox interrupts and not require support for outgoing mailbox interrupts. The interrupt service routine tasks are shown below:
Servicing a PCI mailbox interrupt (INTA#): 1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5935. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). INTCSR INTCSR Bit 16 Bit 17 PCI outgoing mailbox interrupt indicator PCI incoming mailbox interrupt indicator
2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written. MBEF MBEF Bits 31:16 Bits 15:0 Full PCI incoming mailbox bytes Empty PCI outgoing mailbox bytes
3. Access the mailbox. Based on the contents of MBEF, mailboxes are read or written. Reading an incoming mailbox byte clears the corresponding status bit in MBEF. OMBx IMBx Bits 31:0 Bits 31:0 PCI outgoing mailboxes PCI incoming mailboxes
4. Clear the interrupt source. The PCI INTA# signal is deasserted by clearing the interrupt request. The request is cleared by writing a `1' to the appropriate bit. INTCSR INTCSR Bit 16 Bit 17 Clear PCI outgoing mailbox interrupt Clear PCI incoming mailbox interrupt
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Servicing an Add-On mailbox interrupt (IRQ#): 1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5935. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). AINT AINT Bit 16 Bit 17 Add-On incoming mailbox interrupt indicator Add-On outgoing mailbox interrupt indicator
2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written. AMBEF AMBEF Bits 31:16 Bits 15:0 Empty Add-On outgoing mailbox bytes Full Add-On incoming mailbox bytes
3. Access the mailbox. Based on the contents of AMBEF, mailboxes are read or written. Reading an incoming mailbox byte clears the corresponding status bit in AMBEF. AIMBx AOMBx Bits 31:0 Bits 31:0 Add-On incoming mailboxes Add-On outgoing mailboxes
4. Clear the interrupt source. The Add-On IRQ# signal is deasserted by clearing the interrupt request. The request is cleared by writing a `1' to the appropriate bit. AINT AINT Bit 16 Bit 17 Clear Add-On incoming mailbox interrupt Clear Add-On outgoing mailbox interrupt
In both cases, step 3 involves accessing the mailbox. To allow the incoming mailbox interrupt logic to be cleared, the mailbox status bit must also be cleared. Reading an incoming mailbox clears the status bits. Another option for clearing the status bits is to use the Mailbox Flag Reset bit in the MCSR and AGCSTS registers, but this clears all status bits, not just for a single mailbox or mailbox byte. For outgoing mailbox interrupts, the read of a mailbox register is what generated the interrupt; this ensures the status bits are already clear.
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FIFO OVERVIEW
The S5935 has two internal FIFOs. One FIFO is for PCI bus to Add-On bus, the other FIFO is for Add-On bus to PCI bus transfers. Each of these has eight 32bit registers. The FIFOs are both addressed through a single PCI/Add-On Operation Register offset, but which internal FIFO is accessed is determined by whether the access is a read or write. The FIFO may be either a PCI target or a PCI initiator. As a target, the FIFO allows a PCI bus master to access Add-On data. The FIFO also allows the S5935 to become a PCI initiator. Read and write address registers and transfer count registers allow the S5935 to perform DMA transfers across the PCI bus. The FIFO may act as initiator and a target at different times in the same application. The FIFO can be configured to support various AddOn bus configurations. FIFO status and control signals allow simple cascading into an external FIFO, the AddOn bus can be 8-, 16-, or 32-bits wide, and data endian conversion is optional to support any type of Add-On CPU. PCI and Add-On interrupt capabilities are available to support bus mastering through the FIFO. either a PCI target or program it to enable the S5935 to be a PCI initiator (bus master). The following sections describe, on a functional level, the capabilities of the S5935 FIFO interface.
FIFO Buffer Management and Endian Conversion
The S5935 provides a high degree of flexibility for controlling the data flow through the FIFO. Each FIFO (PCI to Add-On and Add-On to PCI) has a specific FIFO advance condition. For FIFO writes, the byte which signifies a location is full is configurable. For FIFO reads, the byte which signifies a location is empty is configurable. This ability is useful for transferring data through the FIFO with Add-Ons which are not 32-bits wide. Endian conversion may also be performed on data passing through the FIFO.
FIFO Advance Conditions
FUNCTIONAL DESCRIPTION
The S5935 FIFO interface allows a high degree of functionality and flexibility. Different FIFO management schemes, endian conversion schemes, and advance conditions allow for a wide variety of Add-On interfaces. Applications may implement the FIFO as
Figure 72. INTCSR FIFO Advance and Endian Control Bits
INTCSR
31 30 29
The specific byte lane used to advance the FIFO, when accessed, is determined individually for each FIFO interface (PCI and Add-On). The control bits to set the advance condition are D29:26 of the Interrupt Control/Status Register (INTCSR) in the PCI Operation Registers (Figure 1). The default FIFO advance condition is set to byte 0. With the default setting, a write to the FIFO with BE0# asserted indicates that the FIFO location is now full, advancing the FIFO pointer to the next location. BE0# does not have to be the only byte enable asserted. Note, the FIFO advance condition may be different for the PCI to Add-On FIFO and the Add-On to PCI FIFO directions.
28 27 26 25 24
PCI TO ADD-ON FIFO PCI ADD-ON DWORD TOGGLE 0 = BYTES 0-3 (DEFAULT) 1 = BYTE 4-7 (NOTE1) ADD-ON TO PCI FIFO ADD-ON PCI DWORD TOGGLE 0 = BYTES 0-3 (DEFAULT) 1 = BYTE 4-7 (NOTE1)
0 0 1 1
0 1 0 1
NO CONVERSION (DEFAULT) 16 BIT ENDIAN CONV. 32 BIT ENDIAN CONV. 64 BIT ENDIAN CONV
NOTE 1: D24 AND D25 MUST BE ALSO "1"
FIFO ADVANCE CONTROL PCI INTERFACE 0 0 BYTE 0 (DEFAULT) 0 1 BYTE 1 1 0 BYTE 2 1 1 BYTE 3 FIFO ADVANCE CONTROL ADD-ON INTERFACE 0 0 BYTE 0 (DEFAULT) 0 1 BYTE 1 1 0 BYTE 2 1 1 BYTE 3
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The configurable FIFO advance condition may be used to transfer data to and from Add-On interfaces which are not 32-bits wide. For a 16-bit Add-On bus, the Add-On to PCI FIFO advance condition can be set to byte 2. This allows a 16-bit write to the lower 16-bits of the FIFO register (bytes 0 and 1) and a second write to the upper 16-bits of the FIFO register (bytes 2 and 3). The FIFO does not advance until the second access. This allows the Add-On to operate with 16-bit data, while the PCI bus maintains a 32-bit data path.
Figure 73. Figure 2a. 16-bit Endian Conversion
DESTINATION D 31-24 D 23-16 D 15-8 D 7-0
Endian Conversion
Bits D31:30 and D25:24 of the INTCSR PCI Operation Register control endian conversion operations for the FIFO (Figure 1). When endian conversion is performed, it affects data passing in either direction through the FIFO interface. Figures 2a and 2b show 16-bit and 32-bit endian conversion. It is important to note that endian conversion is performed on data BEFORE it enters the FIFO. This affects the FIFO advance condition. Example: the FIFO is configured to perform 32-bit endian conversion on data, and the FIFO advance condition is set to byte 0. Byte 3 is written into the FIFO (BE3# asserted). After the endian conversion, byte 3 becomes byte 0, and the FIFO advances. This behavior must be considered when not performing full 32-bit accesses to the FIFO. Figure 2b. 32-bit Endian Conversion
DESTINATION
BYTE 3
BYTE 2
BYTE 1
BYTE 0
D 31-24
D 23-16
D 15-8
D 7-0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
D 31-24
D 23-16
D 15-8
D 7-0
SOURCE
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Notes: 1. During operation, the INTCSR FIFO advance condition bits (D29:26) should only be changed when the FIFO is empty and is idle on both the Add-On and PCI interfaces.
D 31-24
D 23-16
D 15-8
D 7-0
SOURCE
Notes: 1. During operation, the INTCSR FIFO endian conversion bits (D25:24) and 64-bit access bits (D31:30) should only be changed when the FIFO is empty and is idle on both the Add-On and PCI interfaces.
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64-Bit Endian Conversion
Because the S5935 interfaces to a 32-bit PCI bus, special operation is required to handle 64-bit data endian conversion. Figure 2c shows 64-bit endian conversion. The S5935 must know whether the lower 32-bits enter the FIFO first or the upper 32-bits enter the FIFO first. INTCSR D31:30 identify which method is used by the application. These bits toggle after each 32-bit operation to indicate if half or all of a 64-bit data operation has been completed. The initial state of these bits establishes the loading and emptying order for 64-bit data during operation. Figure 2c. 64-bit Endian Conversion
DESTINATION READ ORDER: BYTES 3-0 FIRST OR BYTES 7-4 FIRST SEE TEXT D 31-24 D 23-16 D 15-8 D 7-0
SLR
SLR
SLR
SLR
BYTE 7
BYTE 6
BYTE 5
BYTE 4
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BYTE 7 LOAD ORDER: BYTES 3-0 FIRST OR, BYTES 7-4 FIRST SEE TEXT
BYTE 6
BYTE 5
BYTE 4
BYTE 3
BYTE 2
BYTE 1
BYTE 0
D 31-24
D 23-16
D 15-8
D 7-0
SOURCE
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Add-On FIFO Status Indicators
Signal RDFIFO# WRFIFO# FRC# Function Reads data from the PCI to Add-On FIFO Writes data into the Add-On to PCI FIFO Reset PCI to Add-On FIFO pointers and status indicators1 Reset Add-On to PCI FIFO pointers and status indicators1 Enable bus mastering for Add-On initiated PCI reads1 Enable bus mastering for Add-On initiated PCI writes1
The Add-On interface implements FIFO status pins to indicate the full and empty conditions of the PCI to Add-On and Add-On to PCI FIFOs. These may be used by the Add-On to allow data transfers between the FIFO and memory, a peripheral, or even a cascaded external FIFO. The RDEMPTY and WRFULL status outputs are always available to the Add-On. Additional status signals are multiplexed with the bytewide, non-volatile memory interface pins. If the S5935 is configured for Add-On initiated bus mastering, these status signals also become available to the Add-On. FIFO status is also indicated by bits in the Add-On General Control/Status and Bus Master Control/Status Registers. The table below lists all FIFO status outputs and their functions.
FWC#
AMREN
AMWEN
1. These signals are only available when a serial non-volatile memory is used and the S5935 is configured for Add-On initiated bus mastering.
Signal RDEMPTY WRFULL FRF
Function Indicates empty condition of the PCI to Add-On FIFO Indicates full condition of the Add-On to PCI FIFO Indicates full condition of the PCI to AddOn FIFO1 Indicates the empty condition of the AddOn to PCI FIFO1
PCI Bus Mastering with the FIFO
The S5935 may initiate PCI bus cycles through the FIFO interface. The S5935 allows blocks of data to be transferred to and from the Add-On by specifying a source/destination address on the PCI bus and a transfer byte count. This DMA capability allows data to be transferred across the PCI bus without host CPU intervention. Initiating a bus master transfer requires programming the appropriate address registers and transfer byte counts. This can be done from either the PCI interface or the Add-On interface. Initiating bus master transfers from the add-on is advantageous because the host CPU does not have to intervene for the S5935 to become a PCI Initiator. At the end of a transfer the S5935 may generate an interrupt to either the PCI bus (for PCI initiated transfers) or Add-On interface (for Add-On initiated transfers).
Add-On Initiated Bus Mastering
FWE
1. These signals are only available when a serial non-volatile memory is used and the device is configured for Add-On initiated bus mastering.
Add-On FIFO Control Signals
The Add-On interface implements FIFO control pins to manipulate the S5935 FIFOs. These may be used by Add-On to control data transfer between the FIFO and memory, a peripheral, or even a cascaded external FIFO. The RDFIFO# and WRFIFO# inputs are always available. These pins allow direct access to the FIFO without generating a standard Add-On register access using RD#, WR#, SELECT#, address pins and the byte enables. Additional control signals are multiplexed with the byte-wide, non-volatile memory interface pins. If a serial non-volatile memory is used and the S5935 is configured for Add-On initiated bus mastering, these control signals also become available. For PCI initiated bus mastering, AMREN, AMWEN, FRC#, and FWC# functionality is always available through bits in the Bus Master Control/Status and Add-On General Control/Status Registers. The FIFO control inputs are listed below.
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If bit 7 in location 45h of an external serial non-volatile memory is zero, the Master Read Address Register (MRAR), Master Write Address Register (MWAR), Master Read Transfer Count (MRTC), and Master Write Transfer Count (MWTC) are accessible only from the Add-On interface. Add-On initiated bus mastering is not possible when a byte-wide boot device is used due to shared device pins. When configured for Add-On initiated bus mastering, the S5935 transfers data until the transfer count reaches zero, or it may be configured to ignore the transfer count.
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For bus master transfers initiated by the Add-On interface, some applications may not know the size of the data block to be transferred. To avoid constantly updating the transfer count register, the transfer count may be disabled. Bit 28 in the Add-On General Control/Status Register (AGCSTS) performs this function. Disabling the transfer count also disables the interrupt capabilities. Regardless of whether Add-On transfer count is enabled or disabled, the Add-On Master Read Enable (AMREN) and Add-On Master Write Enable (AMWEN) inputs control when the S5935 asserts or deasserts its request to the PCI bus. When Add-On transfer count is enabled, the S5935 will only request the bus when both the transfer count (read or write) is not zero and the appropriate enable line (AMREN or AMWEN) is active. For Add-On initiated bus mastering, AMWEN and AMREN override the read and write bus mastering enable bits in the Bus Master Control/ Status Register (MCSR).
PCI Initiated Bus Mastering
written before or after bus mastering is enabled. If bus mastering is enabled, no transfer occurs until the transfer count is programmed with a non-zero value. Once a transfer begins, this register is automatically updated to reflect the number of bytes remaining to be transferred. If the transfer count registers are disabled (for Add-On initiated bus mastering), transfers begin as soon as bus mastering is enabled. Although transfers must begin on DWORD boundaries, transfer counts do not have to be multiples of four bytes. For example, if the write transfer count (MWTC) register is programmed with a value of 10 (decimal), the S5935 performs two DWORD writes and a third write with only BE0# and BE1# asserted.
Bus Mastering FIFO Management Schemes
If bit 7 in location 45h of the external non-volatile memory is one, the Master Read Address Register (MRAR), Master Write Address Register (MWAR), Master Read Transfer Count (MRTC), and Master Write Transfer Count (MWTC) are accessible only from the PCI bus interface. In this configuration, the S5935 transfers data until the transfer count reaches zero. The transfer count cannot be disabled for PCI initiated bus mastering. If no external nv memory boot device is used, the S5935 defaults to PCI initiated bus mastering.
Address and Transfer Count Registers
The S5935 provides flexibility in how the FIFO is managed for bus mastering. The FIFO management scheme determines when the S5935 requests the bus to initiate PCI bus cycles. The management scheme is configurable for the PCI to Add-On and Add-On to PCI FIFO (and may be different for each). Bus mastering must be enabled for the management scheme to apply (via the enable bits or AMREN/AMWEN). For the PCI to Add-On FIFO, there are two management options. The PCI to Add-On FIFO management option is programmed through the Bus Master Control/ Status Register (MCSR). The FIFO can be programmed to request the bus when any DWORD location is empty or only when four or more locations are empty. After the S5935 is granted control of the PCI bus, the management scheme does not apply. The device continues to read as long as there is an open FIFO location. When the PCI to Add-On FIFO is full or bus mastering is disabled, the PCI bus request is removed by the S5935. For the Add-On to PCI FIFO, there are two management options. The Add-On to PCI FIFO management option is programmed through the Bus Master Control/ Status Register (MCSR). The FIFO can be programmed to request the bus when any DWORD location is full or only when four or more locations are full. After the S5935 is granted control of the PCI bus, the management scheme does not apply. The device continues to write as long as there is data in the FIFO. When the Add-On to PCI FIFO is empty or bus mastering is disabled, the PCI bus request is removed by the S5935. There are two special cases for the Add-On to PCI FIFO management scheme. The first case is when the FIFO is programmed to request the PCI bus only when four or more locations are full, but the transfer count is less than 16 bytes. In this situation, the FIFO ignores
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The S5935 has two sets of registers used for bus master transfers. There are two operation registers for bus master read operations and two operation registers for bus master write operations. One operation register is for the transfer address (MWAR and MRAR). The other operation register is for the transfer byte count (MWTC and MRTC). The address registers are written with the first address of the transfer before bus mastering is enabled. Once a transfer begins, this register is automatically updated to reflect the address of the current transfer. If a PCI target disconnects from an S5935 initiated cycle, the transfer is retried starting from the current address in the register. If bus grant (GNT#) is removed or bus mastering is disabled (using AMREN or AMWEN), the value in the address register reflects the next address to be accessed. Transfers must begin on DWORD boundaries. The transfer count registers contain the number of bytes to be transferred. The transfer count may be
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the management scheme and finishes transferring the data. The second case is when the S5935 is configured for Add-On initiated bus mastering with transfer counts disabled. In this situation, the FIFO management scheme must be set to request the PCI bus when one or more locations are full. AMREN and AMWEN may be used to implement a specific FIFO management scheme.
FIFO Bus Master Cycle Priority
BUS INTERFACE
The S5935 FIFO may be accessed from the Add-On interface or the PCI interface. Add-On FIFO control and status signals allow a simple interface to the FIFO with either an Add-On CPU or programmable logic. The following section describes the PCI and Add-On interface behavior and hardware interface.
FIFO PCI Interface (Target Mode)
In many applications, the FIFO is used as a PCI initiator performing both PCI reads and writes. This requires a priority scheme be implemented. What happens if the FIFO condition for initiating a PCI read and a PCI write are both met? Bits D12 and D8 in the Bus Master Control/Status Register (MCSR) control the read and write cycle priority, respectively. If these bits are both set or both clear, priority alternates, beginning with a read cycle. If the read priority is set and the write priority is clear, read cycles take priority. If the write priority is set and the read priority is clear, write cycles take priority. Priority arbitration is only done when neither FIFO has control of the PCI bus (the PCI to Add-On FIFO would never interrupt an Add-On to PCI FIFO transfer).
FIFO Generated Bus Master Interrupts
The S5935 FIFO may act as a standard PCI target. FIFO empty/full status may be determined by the PCI initiator by reading the status bits in the PCI Bus Master Control/Status Register (MCSR). The FIFO occupies a single 32-bit register location within the PCI Operation Registers. A PCI initiator may not perform burst accesses to a FIFO as it is a single address. Each data phase of a burst causes the PCI initiator to increment its address counter (even though only the first address is driven at the beginning of the burst). The initiator keeps track of the current address in case a disconnect occurs. This allows the initiator to continue the burst from where the disconnect occurred. If the S5935 FIFO initiated a disconnect during a PCI burst to the FIFO register, the burst would be resumed at an address other than the FIFO location (because the initiator address counter has incremented). The S5935 always signals a disconnect if a burst to any PCI Operation Register is attempted. Because the PCI to Add-On FIFO and the Add-On to PCI FIFO occupy a single location within the PCI and Add-On Operation Registers, which FIFO is accessed is determined by whether the access is a read or write. This means that once data is written into the FIFO, the value written cannot be read back. For PCI reads from the Add-On to PCI FIFO, the S5935 asserts TRDY# and completes the PCI cycle (Figure 3). If the PCI bus attempts to read an empty FIFO, the S5935 immediately issues a disconnect with retry (Figure 4). The Add-On to PCI FIFO status indicators change one PCI clock after a PCI read. For PCI writes to the PCI to Add-On, the S5935 asserts TRDY# and completes the PCI cycle (Figure 5). If the PCI bus attempts to write a full FIFO, the S5935 immediately issues a disconnect with retry (Figure 6). The PCI to Add-On FIFO status indicators change one PCI clock after a PCI write.
Interrupts may be generated under certain conditions from the FIFO. If PCI initiated bus mastering is used, INTA# is generated to the PCI interface. If Add-On initiated bus mastering is used, IRQ# is generated to the Add-On interface. Interrupts may be disabled. FIFO Interrupts may be generated from one or more of the following during bus mastering: read transfer count reaches zero, write transfer count reaches zero, or an error occurs during bus mastering. Error conditions include a target or master abort on the PCI bus. Interrupts on PCI error conditions are only enabled if one or both of the transfer count interrupts are enabled. The Add-On Interrupt Control/Status Register (AINT) or the Interrupt Control Status Register (INTCSR) indicates the interrupt source. The interrupt service routine may read these registers to determine what action is required. As mailboxes are also capable of generating interrupts, this must also be considered in the service routine. Interrupts are also cleared through these registers.
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FIFO PCI Interface (Initiator Mode)
The S5935 can act as an initiator on the PCI bus. This allows the device to gain control of the PCI bus to transfer data to or from the FIFO. Internal address and transfer count registers control the number of PCI transfers and the locations of the transfers. The following paragraphs assume the proper registers and bits are programmed to enable bus mastering.
PCI read and write transfers from the S5935 are very similar. The FIFO management scheme determines when the S5935 asserts its PCI bus request (REQ#). When bus grant (GNT#) is returned, the device begins running PCI cycles. Once the S5935 controls the bus, the FIFO management scheme is not important. It only determines when PCI bus control is initially requested. PCI bus reads and writes are always performed as bursts by the S5935, if possible.
Figure 74. PCI Read from a Full S5935 FIFO
PCI Signals PCI_CLK FRAME# AD[31:0] IRDY# TRDY# DEVSEL# STOP# Add-on Signals WRFULL FWE ADDR DATA
Figure 75. PCI Read from an Empty S5935 FIFO (Target Disconnect)
PCI Signals PCI_CLK FRAME# AD[31:0] IRDY# TRDY# DEVSEL# STOP# Target Disconnect with Retry Add-on Signals WRFULL FWE ADDR DATA
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Figure 76. PCI Write to an Empty S5935 FIFO
PCI Signals PCI_CLK FRAME# AD[31:0] IRDY# TRDY# DEVSEL# STOP# Add-on Signals RDEMPTY FRF ADDR DATA
Figure 77. PCI Write to a Full S5935 FIFO (Target Disconnect)
PCI Signals PCI_CLK FRAME# AD[31:0] IRDY# TRDY# DEVSEL# STOP# Target Disconnect with Retry Add-on Signals RDEMPTY FRF ADDR DATA
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FIFO PCI Bus Master Reads Add-On FIFO Register Accesses
For PCI read transfers (filling the PCI to Add-On FIFO), read cycles are performed until one of the following occurs: - Bus Master Read Transfer Count Register (MRTC), if used, reaches zero - The PCI to Add-On FIFO is full - GNT# is removed by the PCI bus arbiter - AMREN is deasserted If the transfer count is not zero, GNT# remains asserted, and AMREN is asserted, the FIFO continues to read data from the PCI bus until there are no empty locations in the PCI to Add-On FIFO. If the Add-On can empty the FIFO as quickly as it can be filled from the PCI bus, very long bursts are possible. The S5935 deasserts REQ# when it completes the access to fill the last location in the FIFO. Once REQ# is deasserted, it will not be reasserted until the FIFO management condition is met.
FIFO PCI Bus Master Writes
The FIFO may be accessed from the Add-On interface through the Add-On FIFO Port Register (AFIFO) read or write. This is offset 20h in the Add-On Operation Registers. This register is accessed synchronous to BPCLK. To access the FIFO as a normal Add-On Operation Register, ADR[6:2], BE[3:0]#, SELECT#, and RD# or WR# are required. Figure 7 shows a synchronous FIFO register burst access. SELECT# must meet setup and hold times relative to the rising edge of BPCLK. RD# and SELECT# both asserted enables the DQ outputs, and the first data location (data 0) in the FIFO is driven on to the bus. The FIFO address and the byte enables must be valid before valid data is driven onto the DQ bus. Data 0 remains valid until the next rising edge of BPCLK. The rising edge of BPCLK causes the FIFO pointer to advance to the next location (data 1). The next rising edge of BPCLK also advances the FIFO pointer to the next location (data 2). The status outputs reflect the FIFO condition after it advances, and are updated off of the rising edge of BPCLK. When RD# or SELECT# is deasserted, the DQ bus floats. The next time a valid FIFO access occurs and RD# and SELECT# are asserted, data 2 is presented on the DQ bus (as there was no BPCLK edge to advance the FIFO).
Add-On FIFO Direct Access Mode
For PCI write transfers (emptying the Add-On to PCI FIFO), write cycles are performed until one of the following occurs: - Bus Master Write Transfer Count Register (MWTC), if used, reaches zero - The Add-On to PCI FIFO is empty - GNT# is removed by the PCI bus arbiter - AMWEN is deasserted If the transfer count is not zero, GNT# remains asserted, and AMWEN is asserted, The FIFO continues to write data to the PCI bus until there are is no data in the Add-On to PCI FIFO. If the Add-On can fill the FIFO as quickly as it can be emptied to the PCI bus, very long bursts are possible. The S5935 deasserts REQ# when it completes the access to transfer the last data in the FIFO. Once REQ# is deasserted, it will not be reasserted until the FIFO management condition is met.
Add-On Bus Interface
The FIFO register may be accessed in two ways from the Add-On interface. It can be accessed through normal register accesses or directly with the RDFIFO# and WRFIFO# inputs. In addition, the FIFO register can also be accessed synchronous to BPCLK. The Add-On interface also supports datapaths which are not 32-bits. The method used to access the FIFO from the Add-On interface is independent of whether the FIFO is a PCI target or a PCI initiator.
Instead of generating an address, byte enables, SELECT# and a RD# or WR# strobe for every FIFO access, the S5935 allows a simple, direct access mode. Using RDFIFO# and WRFIFO# is functionally identical to performing a standard AFIFO Port Register access, but requires less logic to implement. Accesses to the FIFO register using the direct access signals are always 32-bits wide. The only exception to this is when the MODE pin is configured for 16-bit operation. In this situation, all accesses are 16-bits wide. The RD# and WR# inputs must be inactive when RDFIFO# or WRFIFO# is active. The ADR[6:2] and BE[3:0]# inputs are ignored. RDFIFO# and WRFIFO# act as enables with BPCLK acting as the clock. A Synchronous interface allows higher data rates. Figure 8 shows a synchronous FIFO register direct burst access using RDFIFO#. RDFIFO# acts as an enable and the first data location (data 0) in the FIFO is driven on to the bus when RDFIFO# is asserted. Data 0 remains valid until the next rising edge of BPCLK. The rising edge of BPCLK causes the FIFO pointer to advance to the next location (data 1). The next rising edge of BPCLK advances the FIFO pointer to the next location (data 2). The status outputs reflect
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the FIFO condition after it advances, and are updated off of the rising edge of BPCLK. When RDFIFO# is deasserted, the DQ bus floats. The next time RDFIFO# is asserted, data 2 is presented on the DQ bus (as there was no BPCLK edge to advance the FIFO). A synchronous FIFO interface has the advantage of allowing data to be accessed more quickly (in bursts) by the Add-On. As a target, if a full S5935 FIFO is written (or an empty FIFO is read) by a PCI initiator, the S5935 requests a retry. The faster the Add-On interface can empty (or fill) the FIFO, the less often retries occur. With the S5935 as a PCI initiator, a similar situation occurs. Not emptying or filling the FIFO quickly enough results in the S5935 giving up control of the PCI bus. Higher PCI bus data transfer rates are possible through the FIFO with a synchronous interface.
Figure 78. Synchronous FIFO Register Burst Read Access Example
FIFO Pointer Advances BPCLK BE[3:0]# ADR[6:2] DQ[31:0] SELECT# RD# RDEMPTY Status Before Read New Status New Status Valid Byte Enables Valid Address Data 0 Data 1 Data 2
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Additional Status/Control Signals for Add-On Initiated Bus Mastering Inputs:
EQ (7) AMWEN Add-On bus Mastering Write ENable: This input is driven high to enable bus master writes. EQ (6) AMREN Add-On bus Mastering Read ENable: This input is driven high to enable bus master reads. EQ (5) FRC# FIFO Read Clear: This line is driven low to clear the PCI to Add-On FIFO. EQ (4) FWC# FIFO Write Clear: This line is driven low to clear the Add-On to PCI FIFO. FRF (PCI to Add-On FIFO full) and FWE (Add-On to PCI FIFO empty) supplement the RDEMPTY and WRFULL status indicators. These additional status outputs provide additional FIFO status information for Add-On FIFO control logic.
If a serial non-volatile memory is used to configure the S5935, and the device is configured for Add-On initiated bus mastering, two additional FIFO status signals and four additional control signals are available to the Add-On interface. The FRF and FWE outputs provide additional FIFO status information. Inputs FRC#, FWC#, AMREN, and AMWEN provide additional FIFO control. Applications may use these signals to monitor/ control FIFO flags and PCI bus requests. These new signals are some of the lines that were used for bytewide nvram interface, but now are reconfigured. The reconfigured lines are as follows:
Outputs:
E_ADDR (15) FRF FIFO Read Full: Indicates that the PCI to Add-On FIFO is full. E_ADDR (14) FWE FIFO Write Empty: Indicates the last Add-On to PCI FIFO. Data has transferred to a final buffer and is queued for transfer, FIFO is empty.
Figure 79. Synchronous FIFO Register Burst RDFIFO# Access Example
FIFO Pointer Advances BPCLK DQ[31:0] RDFIFO# RDEMPTY Status Before Read New Status New Status Data 0 Data 1 Data 2
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The FRC# and FWC# inputs allow Add-On logic to reset the PCI to Add-On or Add-On to PCI FIFO flags. The FIFO flags can always be reset with software through the Add-On General Control/Status Register (AGCSTS) or the Bus Master Control/Status Register (MCSR), but these hardware inputs are useful for designs which do no implement a CPU on the Add-On card. Asserting the FRC# input resets the PCI to AddOn FIFO. Asserting the FWC# input re-sets the AddOn to PCI FIFO. The AMREN and AMWEN inputs allow Add-On logic to individually enable and disable bus mastering for the PCI to Add-On and Add-On to PCI FIFO. These inputs override the Bus Master Control/Status Register (MCSR) bus master enable bits. The S5935 may request the PCI bus for the PCI to Add-On FIFO when AMREN is asserted and may request the PCI bus for the Add-On to PCI FIFO when AMWEN is asserted. If AMREN or AMWEN is deasserted, the S5935 removes its PCI bus request and gives up control of the bus. AMREN and AMWEN are useful for Add-Ons with external FIFOs cascaded into the S5935. For PCI bus master write operations, the entire S5935 Add-On to PCI FIFO and the external FIFO may be filled before enabling bus mastering, providing a single long burst write rather than numerous short bursts. In some applications, the amount of data to be transferred is not known. During read operations, the S5935, attempting to fill its PCI to Add-On FIFO, may access up to eight memory locations beyond what is required by the Add-On before it stops. In this situation, AMREN can be deasserted to disable PCI reads, and then FRC# can be asserted to flush the unwanted data from the FIFO.
FIFO Generated Add-On Interrupts
used, this must be considered in the interrupt service routine.
8-Bit and 16-Bit FIFO Add-On Interfaces
The S5935 FIFO may also be used to transfer data between the PCI bus and 8-bit or 16-bit Add-On interfaces. This can be done using FIFO advance conditions or the S5935 MODE input pin. The FIFO may be used as an 8-bit or 16-bit wide FIFO. To use the FIFO as an 8-bit interface, the advance condition should be set for byte 0 (no data is transferred in the upper 3 bytes). To use the FIFO as a 16-bit interface, the advance condition should be set for byte 1 (no data is transferred in the upper 2 bytes). This allows a simple Add-On bus interface, but it has the disadvantage of not efficiently utilizing the PCI bus bandwidth because the host is forced to perform 8-bit or 16-bit accesses to the FIFO on the PCI bus. This is the only way to communicate with an 8-bit Add-On through the FIFO without additional logic to steer byte lanes on the Add-On data bus. Pass-Thru mode is more suited to 8-bit Add-On interfaces. Implementing a 16-bit wide FIFO is a reasonable solution, but to avoid wasting PCI bus bandwidth, the best method is to allow the PCI bus and the FIFO to operate with 32-bit data. The S5935 can assemble or disassemble 32-bit quantities for the Add-On interface. This is possible through the MODE pin. When MODE is low, the Add-On data bus is 32-bits. When MODE is high, the Add-On data bus is 16-bits. When MODE is configured for 16-bit operation, BE3# becomes ADR1. With the FIFO direct access signals (RDFIFO# and WRFIFO#), the MODE pin must reflect the actual AddOn data bus width. With MODE = 16-bits, the S5935 automatically takes two consecutive, 16-bit Add-On writes to the FIFO and assembles a 32-bit value. FIFO reads operate in the same manner. Two consecutive Add-On reads empty the 32-bit FIFO register. The 16bit data bus is internally steered to the lower and upper words of the 32-bit FIFO register. One consideration needs to be taken when using the FIFO direct access signals and letting the S5935 do byte lane steering internally. The default condition used to advance the FIFO is byte 0. This must be changed to byte 2 or 3. When MODE is configured for a 16-bit Add-On bus, the first 16-bit cycle to the FIFO always accesses the low 16-bits. If the FIFO advance condition is left at byte 0, the FIFO advances after the first 16-bit cycle and the data in the upper 16-bits is directed to the next FIFO location, shifting the data.
For Add-On initiated bus mastering, the S5935 may be configured to generate interrupts to the Add-On interface for the following situations: - Read transfer count reaches zero - Write transfer count reaches zero - An error occurred during the bus master transaction The interrupt is posted to the Add-On interface with the IRQ# output. A high-to-low transition on this output indicates an interrupt condition. Because there is a single interrupt output and multiple interrupt conditions, the Add-On Interrupt Control/Status Register (AINT) must be read to determine the interrupt source. This register is also used to clear the interrupt, returning IRQ# to its high state. If mailbox interrupts are also
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Some applications hold the RDFIFO# and WRFIFO# inputs active for a synchronous interface. In 16-bit mode, designs must avoid writing to a full FIFO. The data for the write is lost, but the internal mechanism to direct the 16-bit external data bus to the upper 16-bits of the FIFO register is triggered. This creates a situation where the FIFO is out of step. The next 16-bit FIFO write is directed to the upper 16-bits of the FIFO, and the FIFO advances incorrectly. The WRFULL output should be used to gate the WRFIFO# input to avoid this situation. A similar problem can occur if Add-On logic attempts to read an empty FIFO in 16-bit mode. RDEMPTY should be used to gate the RDFIFO# input to avoid problems with the FIFO getting out of step. In 32-bit mode (MODE = low), these situations do not occur. If FIFO accesses are done without the direct access signals with MODE configured for 16-bits (using ADR, SELECT#, etc.), external hardware must toggle ADR1 between consecutive 16-bit bus cycles. The FIFO advance condition must be set to correspond to the order the application accesses the upper and lower words in the FIFO register. Bits 6 and 5 in location 45h enable FIFO register accesses using the RDFIFO#, WRFIFO#, RD# and WR# inputs synchronous to BPCLK. For synchronous operation, RDFIFO#, WRFIFO#, RD# and WR# operate as enables, using BPCLK to clock data.
Location 45h Configuration Bits Bit 7 0 1 Bit 6 0 1 Bit 5 0 1 Bus Master Register Access Address and transfer count registers only accessible from the Add-On interface Address and transfer count registers only accessible from the PCI interface (default) RDFIFO#, RD# Operation Enable - RDFIFO# and RD# functions. Not allowed. Must be 0. WRFIFO#, WR# Operation Enable - WRFIFO# and WR# functions. Not allowed. Must be 0. Target Latency Timer Enable Disable PCI Latency Timer Time Out - Will not disconnect with retry if cannot issue TRDY in specified time Enable PCI Latency Timer Time Out - Will be PCI 2.1 compliant
CONFIGURATION
The FIFO configuration takes place during initialization and during operation. During initialization, the bus master register access rights are defined. During operation, FIFO advance conditions, endian conversion, and bus mastering capabilities are defined. The following section describes the bits and registers which are involved with controlling and monitoring FIFO operation.
FIFO Setup During Initialization
Bit 0 0
1
FIFO Status and Control Bits
Location 45h in an external non-volatile memory may be used to configure the S5935 FIFO during initialization. If no external non-volatile memory is used, FIFO operation is disabled. The value of bit 7 in location 45h determines if the address and transfer count registers used in bus mastering are accessible from the PCI bus or from the Add-On bus. Once the configuration information is downloaded from non-volatile memory after reset, the bus mastering initialization method can not be changed. Access to the bus master address and transfer count registers cannot be alternated between the PCI bus and the Add-On interface during operation.
The FIFO status can be monitored and the FIFO operation controlled from the PCI Operation Registers and/ or the Add-On Operation Registers. The FIFO register resides at offset 20h in the PCI and Add-On Operation Registers. The Bus Master Control/Status (MCSR) PCI Operation register allows a PCI host to monitor FIFO activity and control FIFO operation. Reset controls allow the PCI to Add-On FIFO and Add-On to PCI FIFO flags to be reset (individually). Status bits indicate if the PCI to Add-On FIFO is empty, has four or more open spaces, or is full. Status bits also indicate if the Add-On to PCI FIFO is empty, has four or more full locations or is full. Finally, FIFO PCI bus mastering is monitored/controlled though this register.
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The Add-On General Control/Status (AGCSTS) AddOn Operation Register allows an Add-On CPU to monitor FIFO activity and control FIFO operation. Reset controls allow the PCI to Add-On FIFO and Add-On to PCI FIFO flags to be reset (individually). Status bits indicate if the PCI to Add-On FIFO is empty, has four or more open spaces, or is full. Status bits also indicate if the Add-On to PCI is empty, has four or more full spaces or is full. FIFO bus mastering status may be monitored through this register, but all bus master configuration is through the MCSR PCI Operation Register.
PCI Initiated FIFO Bus Mastering Setup
3. Define FIFO management scheme. These bits define what FIFO condition must exist for the PCI bus request (REQ#) to be asserted by the S5935.
MCSR MCSR Bit 13 Bit 9 PCI to Add-On FIFO management scheme Add-On to PCI FIFO management scheme
For PCI initiated bus mastering, the PCI host sets up the S5935 to perform bus master transfers. The following tasks must be completed to setup FIFO bus mastering: 1. Define interrupt capabilities. The PCI to Add-On and/or Add-On to PCI FIFO can generate a PCI interrupt to the host when the transfer count reaches zero.
INTCSR INTCSR Bit 15 Bit 14 Enable Interrupt on read transfer count equal zero Enable Interrupt on write transfer count equal zero
4. Define PCI to Add-On and Add-On to PCI FIFO priority. These bits determine which FIFO has priority if both meet the defined condition to request the PCI bus. If these bits are the same, priority alternates, with read accesses occurring first.
MCSR MCSR Bit 12 Bit 8 Read vs. write priority Write vs. read priority
5. Define transfer source/destination address. These registers are written with the first address that is to be accessed by the S5935. These address registers are updated after each access to indicate the next address to be accessed. Transfers must start on DWORD boundaries.
MWAR All All Bus master write address Bus master read address
2. Reset FIFO flags. This may not be necessary, but if the state of the FIFO flags is not known, they should be initialized.
MCSR MCSR Bit 26 Bit 25 Reset Add-On to PCI FIFO flags Reset PCI to Add-On FIFO flags
MRAR
6. Define transfer byte counts. These registers are written with the number of bytes to be transferred. The transfer count does not have to be a multiple of four bytes. These registers are updated after each transfer to reflect the number of bytes remaining to be transferred.
MWTC MRTC All All Write transfer byte count Read transfer byte count
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7. Enable Bus Mastering. Once steps 1-6 are completed, the FIFO may operate as a PCI bus master. Read and write bus master operation may be independently enabled or disabled.
MCSR MCSR Bit 14 Bit 10 Enable PCI to Add-On FIFO bus mastering Enable Add-On to PCI FIFO bus mastering
Add-On Initiated FIFO Bus Mastering Setup For AddOn initiated bus mastering, the Add-On sets up the S5935 to perform bus master transfers. The following tasks must be completed to setup FIFO bus mastering: 1. Define transfer count abilities. For Add-On initiated bus mastering, transfer counts may be either enabled or disabled. Transfer counts for read and write operations cannot be individually enabled.
AGCSTS Bit 28 Enable transfer count for read and write bus master transfers
The order of the tasks listed above is not particularly important. It is recommended that bus mastering be enabled as the last step. Some applications may choose to leave bus mastering enabled and start transfers by writing a non-zero value to the transfer count registers. This also works, provided the entire transfer count is written in a single access. As a number of the configuration bits and the two enable bits are all in the MCSR register, it may be most efficient for the FIFO configuration bits to be set with the same register access that enables bus mastering. If interrupts are enabled, a host interrupt service routine is also required. The service routine determines the source of the interrupt and resets the interrupt. As mailbox registers may also be configured to generate interrupts, the exact source of the interrupt is indicated in the PCI Interrupt Control/Status Register (INTCSR). Typically, the interrupt service routine is used to setup the next transfer by writing new addresses and transfer counts, but some applications may also require other actions. If read transfer or write transfer complete interrupts are enabled, master and target abort interrupts are automatically enabled. These indicate a transfer error has occurred. Writing a one to these bits clears the corresponding interrupt.
INTCSR INTCSR INTCSR INTCSR Bit 21 Bit 20 Bit 19 Bit 18 Target abort caused interrupt Master abort caused interrupt Read transfer complete caused interrupt Write transfer complete caused interrupt
2. Define interrupt capabilities. The PCI to Add-On and/or Add-On to PCI FIFO can generate an interrupt to the Add-On when the transfer count reaches zero (if transfer counts are enabled).
AINT AINT Bit Bit 14 15 Enable interrupt on read transfer count equal zero Enable interrupt on write transfer count equal zero
3. Reset FIFO flags. This may not be necessary, but if the state of the FIFO flags is not known, they should be initialized.
AGCSTS AGCSTS Bit 25 Bit 26 Reset Add-On to PCI FIFO flags Reset PCI to Add-On FIFO flags
4. Define FIFO management scheme. These bits define what FIFO condition must exist for the PCI bus request (REQ#) to be asserted by the S5935. This must be programmed through the PCI interface.
MCSR MCSR Bit 13 Bit 9 PCI to Add-On FIFO management scheme Add-On to PCI FIFO management scheme
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5. Define PCI to Add-On and Add-On to PCI FIFO priority. These bits determine which FIFO has priority if both meet the defined condition to request the PCI bus. If these bits are the same, priority alternates, with read accesses occurring first. This must be programmed through the PCI interface.
MCSR MCSR Bit 12 Bit 8 Read vs. write priority Write vs. read priority
interrupt. As mailbox registers may also be configured to generate interrupts, the exact source of the interrupt is indicated in the Add-On Interrupt Control Register (AINT). Typically, the interrupt service routine is used to setup the next transfer by writing new addresses and transfer counts (if enabled), but some applications may also require other actions. If read transfer or write transfer complete interrupts are enabled, the master/ target abort interrupt is automatically enabled. These indicate a transfer error has occurred. Writing a one to these bits clears the corresponding interrupt.
AINT AINT AINT Bit 21 Bit 19 Bit 18 Master/target abort caused interrupt Read transfer complete caused interrupt Write transfer complete caused interrupt
6. Define transfer source/destination address. These registers are written with the first address that is to be accessed by the S5935. These address registers are updated after each access to indicate the next address to be accessed. Transfers must start on DWORD boundaries. MWARAllBus master write address MRARAllBus master read address 7. Define transfer byte counts. These registers are written with the number of bytes to be transferred. The transfer count does not have to be a multiple of four bytes. These registers are updated after each transfer to reflect the number of bytes remaining to be transferred. If transfer counts are disabled, these registers do not need to be programmed.
MWTC MRTC All All Write transfer byte count Read transfer byte count
PASS-THRU OVERVIEW
The S5935 provides a simple registered access port to the PCI bus. Using a handshaking protocol with AddOn card logic, the PCI bus directly accesses resources on the Add-On. The Pass-Thru data transfer method is very useful for direct Add-On memory access, or accessing registers within peripherals on an Add-On board. Pass-Thru operation requires an external nv memory boot device to define and configure the S5935 Pass-Thru regions. The S5935 provides four user-configurable Pass-Thru regions. Each region corresponds to a PCI Configuration Base Address Register (BADR1-4). A region represents a block of address space (the block size is user-defined). Each block can be mapped into memory or I/O space. Memory mapped regions can request to be located below 1 MByte (Real Mode address space for a PC). Each region also has a configurable bus width for the Add-On bus interface. An 8-, 16-, or 32-bit Add-On interface may be selected, for use with a variety of Add-On memory or peripheral devices. Pass-Thru features can be used only when the S5935 is a PCI target. As a target, the S5935 Pass-Thru mode supports single data transfers as well as burst transfers. When accessed with burst transfers, the S5935 supports data transfers at the full PCI bandwidth. The data transfer rate is only limited by the PCI initiator performing the access and the speed of the Add-On logic.
8. Enable Bus Mastering. Once steps 1-7 are completed, the FIFO may operate as a PCI bus master. Read and write bus master operation may be independently enabled or disabled. The AMREN and AMWEN inputs control bus master enabling for Add-On initiated bus mastering. The MCSR bus master enable bits are ignored for Add-On initiated bus mastering. It is recommended that bus mastering be enabled as the last step. Some applications may choose to leave bus mastering enabled (AMREN and AMWEN asserted) and start transfers by writing a non-zero value to the transfer count registers (if they are enabled). If interrupts are enabled, an Add-On CPU interrupt service routine is also required. The service routine determines the source of the interrupt and resets the
FUNCTIONAL DESCRIPTION
To provide the PCI bus Add-On with direct access to Add-On resources, the S5935 has an internal PassDS1527 149
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Thru Address Register (APTA), and a Pass-Thru Data Register (APTD). These registers are connected to both the PCI bus interface and the Add-On bus interface. This allows a PCI initiator to perform Pass-Thru writes (data transferred from the PCI bus to the AddOn bus) or Pass-Thru reads (PCI bus requests data from the Add-On bus). The S5935 Pass-Thru interface supports both single cycle (one data phase) and burst accesses (multiple data phases).
Pass-Thru Transfers
bus performs burst accesses, the APTA register is updated by the S5935 to reflect the address of the current data phase. For PCI writes to the Add-On, the S5935 transfers the data from the PCI bus into the Pass-Thru Data Register (APTD). The S5935 captures the data from the PCI bus when TRDY# is asserted. The PCI bus then becomes available for other transfers. When the PassThru data register becomes full, the S5935 asserts the Pass-Thru status signals to indicate to the Add-On that data is present. The Add-On logic may read the data register and assert PTRDY# to indicate the current access is complete. Until the current access completes, the S5935 responds to further Pass-Thru accesses with retries. For PCI reads from the Add-On, the S5935 asserts the Pass-Thru status signals to indicate to the Add-On that data is required. The Add-On logic should write to the Pass-Thru Data Register and assert PTRDY# to complete the access. The S5935 does not assert TRDY# to the PCI bus until PTRDY# is asserted by Add-On logic. If the Add-On cannot provide data quickly enough, the S5935 signals a retry to the PCI bus. This allows the PCI bus to perform other tasks, rather than waiting for a slow target.
Data transfers between the PCI bus and the Add-On using the Pass-Thru interface are implemented with a handshaking scheme. If the PCI bus writes to an S5935 Pass-Thru region, Add-On logic must read the data from the S5935 and store it on the Add-On. If the PCI bus reads from a Pass-Thru region, Add-On logic must write data to the S5935. Some applications may require that an address be passed to the Add-On for Pass-Thru accesses. For example, a 4 Kbyte Pass-Thru region on the PCI bus may correspond to a 4 Kbyte block of SRAM on the Add-On card. If a PCI initiator accessed this region, the Add-On would need to know the offset within the memory device to access. The Pass-Thru Address Register (APTA) allows the Add-On to access address information for the current PCI cycle. When the PCI
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Pass-Thru Status/Control Signals
BUS INTERFACE
The Pass-Thru interface on the S5935 is a PCI targetonly function. Pass-Thru operation allows PCI initiators to read or write resources on the Add-On card. A PCI initiator may access the Add-On with single data phase cycles or multiple data phase bursts. The Add-On interface implements Pass-Thru status and control signals used by logic to complete data transfers initiated by the PCI bus. The Pass-Thru interface is designed to allow Add-On logic to function without knowledge of PCI bus activity. Add-On logic only needs to react to the Pass-Thru status outputs. The S5935 PCI interface independently interacts with the PCI initiator to control data flow between the devices. The following sections describe the PCI and Add-On bus interfaces. The PCI interface description provides a basic overview of how the S5935 interacts with the PCI bus, and may be useful in system debugging. The Add-On interface description indicates functions required by Add-On logic and details the Pass-Thru handshaking protocol.
PCI Bus Interface
The S5935 Pass-Thru registers are accessed using the standard Add-On register access pins. The PassThru Address Register (APTA) can, optionally, be accessed using a single, direct access input, PTADR#. Pass-Thru cycle status indicators are provided to control Add-On logic based on the type of Pass-Thru access occurring (single cycle, burst, etc.). The following signals are provided for Pass-Thru operation:
Signal PTATN# PTBURST# PTNUM[1:0] PTBE[3:0]# Function This output indicates a Pass-Thru access is occurring This output indicates the Pass-Thru access is a PCI burst access These outputs indicate which Pass-Thru region decoded the PCI address These outputs indicate which data bytes are valid (PCI writes), or requested (PCI reads) This output indicates if the Pass-Thru access is a PCI read or a write When asserted, this input drives the Pass-Thru Address Register contents onto the Add-On data bus When asserted, this input indicates the current Pass-Thru transfer has been completed by the Add-On Buffered PCI bus clock output (to synchronize Pass-Thru data register accesses)
PTWR PTADR#
PTRDY#
BPCLK
The S5935 decodes all PCI bus cycle addresses. If the address associated with the current cycle is to one of S5935 Pass-Thru regions, DEVSEL# is asserted. If the Pass-Thru logic is currently idle (not busy finishing a previous Pass-Thru operation), the bus cycle type is decoded and the Add-On Pass-Thru status outputs are set to initiate a transfer on the Add-On side. If the Pass-Thru logic is currently busy completing a previous access, the S5935 signals a retry to PCI initiator. The following sections describe the behavior of the PCI interface for Pass-Thru accesses to the S5935. Single cycle accesses, burst accesses, and target-initiated retries are detailed.
PCI Pass-Thru Single Cycle Accesses
Pass-Thru Add-On Data Bus Sizing
Many applications require an 8-bit or 16-bit Add-On bus interface. Pass-Thru regions can be configured to support bus widths other than 32-bits. Each Pass-Thru region can be defined, during initialization, as 8, 16-, or 32-bits. All of the regions do not need to be the same. This feature allows a simple interface to 8-and 16-bit Add-On devices. To support alternate Add-On bus widths, the S5935 performs internal data bus steering. This allows the Add-On interface to assemble and disassemble 32-bit PCI data using multiple Add-On accesses to the PassThru Data Register (APTD). The Add-On byte enable inputs (BE[3:0]#) are used to access the individual bytes or words within APTD.
Single cycle transfers are the simplest PCI bus transaction. Single cycle transfers have an address phase and a single data phase. The PCI bus transaction starts when an initiator drives address and command information onto the PCI bus and asserts FRAME#. The initiator always deasserts frame before the last data phase. For single cycle transfers, FRAME# is only asserted during the address phase (indicating the first data phase is also the last). When the S5935 sees FRAME# asserted, it samples the address and command information to determine if the bus transaction is intended for it. If the address is within one of the defined Pass-Thru regions, the S5935 accepts the transfer (assert DEVSEL#), and
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stores the PCI address in the Pass-Thru Address Register (APTA). For Pass-Thru writes, the S5935 responds immediately (asserting TRDY#) and transfers the data from the PCI bus into the Pass-Thru Data Register (APTD). The S5935 then indicates to the Add-On interface that a Pass-Thru write is taking place and waits for Add-On logic to read the APTD register and complete the transfer (assert PTRDY#). Once the S5935 has captured the data from the PCI bus, the transfer is finished from the PCI bus perspective, and the PCI bus becomes available for other transfers. For Pass-Thru reads, the S5935 indicates to the AddOn interface that a Pass-Thru read is taking place and waits for Add-On logic to write the Pass-Thru Data Register and complete the transfer (assert PTRDY#). The S5935 completes the cycle when data is written into the data register. If the Add-On cannot complete the write quickly enough, the S5935 requests a retry from the initiator. See target-requested disconnect information.
PCI Pass-Thru Burst Accesses PCI Retry Conditions
In some applications, Add-On logic may not be able to respond to Pass-Thru accesses quickly. In this situation, the S5935 disconnects from the PCI bus, signaling a retry. This indicates that the initiator should try the access again at a later time. This allows other PCI cycles to be run while the logic on the slow target completes the Pass-Thru access. Ideally, when the initiator retries the access, the target has completed the access and can respond to the initiator. With many devices, particularly memories, the first access takes longer than subsequent accesses (assuming they are sequential and not random). For this reason, the PCI specification allows 16 clocks to respond to the first data phase of a PCI cycle and 8 clocks for subsequent data phases (in the case of a burst) before a retry must be requested by the S5935. The S5935 also requests a retry if an initiator attempts to burst past the end of a Pass-Thru region. The S5935 updates the Pass-Thru Address Register (APTA) for each data phase during bursts, and if the updated address is not within the current Pass-Thru region, a retry is requested. For example, a PCI system may map a 512 byte PassThru memory region to 0DC000h to 0DC1FFh. A PCI initiator attempts a four DWORD burst with a starting address of 0DC1F8h. The first and second data phases complete (filling the DWORDs at 0DC1F8h and 0DC1FCh), but the third data phase causes the S5935 to request a retry. This forces the initiator to present the address 0DC200h on the PCI bus. If this address is part of another S5935 Pass-Thru region, the device accepts the access.
PCI Write Retries
For PCI Pass-Thru burst accesses, the S5935 captures the PCI address and determines if it falls into one of the defined Pass-Thru regions. Accesses that fall into a Pass-Thru region are accepted by asserting DEVSEL#. The S5935 monitors FRAME# and IRDY# on the PCI bus to identify burst accesses. If the PCI initiator is performing a burst access, the Pass-Thru status indicators notify Add-On logic. For Pass-Thru burst writes, the S5935 responds immediately (asserting TRDY#). The S5935 transfers the first data phase of the burst into the Pass-Thru Data Register (APTD), and stores the PCI address in the Pass-Thru Address Register (APTA). The Add-On interface completes the transfer and asserts PTRDY#. Every time PTRDY# is asserted by the Add-On, the S5935 begins the next data phase. The next data phase is latched into the data register. For burst accesses, APTA is automatically incremented by the S5935 for each data phase. For Pass-Thru burst reads, the S5935 claims the PCI cycle (asserting DEVSEL#). The request for data is passed on to Add-On logic and the PCI address is stored in the APTA register. The Add-On interface completes the transfer and asserts PTRDY#. The S5935 then drives the requested data on the PCI bus and asserts TRDY# to begin the next data phase. The APTA register is automatically incremented by the S5935 for each data phase.
When the S5935 requests a retry for a PCI Pass-Thru write, it indicates that the Add-On is still completing a previous Pass-Thru write access. The Pass-Thru Address and Data Register contents (APTA and APTD) are still required for the previous Pass-Thru operation and cannot be updated by the PCI interface until the access completes (the Add-On asserts PTRDY#). When the Add-On is busy completing a Pass-Thru write, the S5935 requests an immediate retry for all Pass-Thru region accesses, allowing the PCI bus to perform other operations. PCI Operation Registers may be accessed while the Add-On is still completing a Pass-Thru access. Only Pass-Thru region accesses receive retry requests.
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PCI Read Retries Add-On Bus Interface
When the S5935 requests a retry for a PCI Pass-Thru read, it indicates that the Add-On could not complete the read in the required time. The Pass-Thru data cannot be read by the PCI interface until the Add-On asserts PTRDY#, indicating the access is complete. If the retry occurs after the Add-On has completed the Pass-Thru operation by writing the appropriate data into the Pass-Thru data register and asserting PTRDY#, the S5935 asserts DEVSEL# and TRDY# to complete the PCI read. If the Add-On still has not completed the Pass-Thru read, the S5935 waits for the required 16 clocks. If the Add-On completes the access during this time, TRDY# is asserted and the access is finished. If the Add-On cannot complete the access within 16 clocks, another retry is requested. When the Add-On is busy completing a Pass-Thru read, the S5935 requests an immediate retry for all Pass-Thru region accesses, except the region currently completing the previous access. This allows the PCI bus to perform other operations. The next access to the Pass-Thru region which initiated the retry must be to the same address which caused the retry. Another initiator accessing the same Pass-Thru region causes the S5935 to respond with the original initiator's data (for reads). S5935 PCI Operation Registers may be accessed while the Add-On is still completing a Pass-Thru access. Only other Pass-Thru region accesses receive retry requests.
Figure 80. Single Cycle Pass-Thru Write
012345 BPCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# SELECT# ADR[6:2] BE[3:0]# RD# DQ[31:0] PTRDY#
The Pass-Thru address and data registers can be accessed as Add-On operation registers. The interface to the Pass-Thru registers is described in. The Pass-Thru data register is updated on the rising edge of BPCLK. For this reason, all Pass-Thru inputs must be synchronous to BPCLK. In the following sections the Add-On Pass-Thru interface is described for PassThru single cycle accesses, burst accesses, targetrequested retries, and when using 8-bit and 16-bit Add-On data buses.
Single Cycle Pass-Thru Writes
A single cycle Pass-Thru write operation occurs when a PCI initiator writes a single value to a Pass-Thru region. PCI single cycle transfers consists of an address phase and one data phase. During the address phase of the PCI transfer, the S5935 stores the PCI address into the Pass-Thru Address Register (APTA). If the S5935 determines that the address is within one of its defined Pass-Thru regions, it captures the PCI data into the Pass-Thru Data Register (APTD). Figure 1 shows a single cycle Pass-Thru write access (Add-On read). The Add-On must read the data stored in the APTD register and transfer it to its destination. Note: RD# may be asserted for multiple clocks to allow interfacing with slow Add-On devices. Data remains valid until PTRDY# is asserted.
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PT DATA
PCI Write cycle completed
Note: For all Add-On accesses using PTADR for address data when in 16 bit mode, ADR[1] must be held low to get the low address word.
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Clock 0: Clock 1: Clock 2: The PCI bus cycle address information is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as a write to Pass-Thru region 1. The PCI data is stored in the S5935 Pass-Thru Data Register. PTATN# is asserted to indicate a Pass-Thru access is occurring. Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# Deasserted. The access has a single data phase. 01. Indicates the PCI access is to Pass-Thru region 1. Asserted. The Pass-Thru access is a write. 0h. Indicates the Pass-Thru access is 32-bits.
SELECT#, address and byte enable inputs are driven to read the Pass-Thru Data Register at offset 2Ch. DQ[31:0] are driven after RD# and SELECT# are asserted. Clock 3: Clock 4: If PTRDY# is asserted at the rising edge of clock 3, PTATN# is immediately deasserted and the Pass-Thru access is completed at clock 4. If Add-On logic requires more time to read the Pass-Thru Data Register (slower memory or peripherals), PTRDY# can be delayed, extending the cycle. With PTRDY# asserted at the rising edge of clock 4, PTATN# is deasserted and the Pass-Thru access is completed at clock 5. PTATN# and PTBURST# deasserted at the rising edge of clock 5 indicates the Pass-Thru access is complete. The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 6.
Clock 5:
Figure 2 shows a single cycle Pass-Thru write using the Pass-Thru address information. This provides PCI cycle address information to select a specific address location within an Add-On memory or peripheral. AddOn logic must latch the address for use during the data transfer. Typically, the entire 32-bit address is not required. The Add-On may implement a scheme where only the required number of address bits are
Figure 81. Single Cycle Pass-Thru Write with PTADR#
012345 BPCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# SELECT# ADR[6:2] BE[3:0]# RD# DQ[31:0] PTRDY# PTADR# 2Ch 0h 0h 1
latched. It may also be useful to use the Pass-Thru region identifiers, PTNUM[1:0] as address lines. For example, Pass-Thru region 1 might be a 64K block of SRAM for data, while Pass-Thru region 2 might be 64K of SRAM for code storage (down-loaded from the host during initialization). Using PTNUM0 as address line A16 allows two unique Add-On memory regions to be defined.
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PT ADDR
PT DATA
PCI Write cycle completed
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The Add-On PTADR# input directly accesses the Pass-Thru Address Register and drives the contents onto the data bus (no BPCLK rising edge is required). The byte enables, address, and SELECT# inputs are ignored when PTADR# is asserted. RD# and WR# must not be asserted when PTADR# is asserted.
Clock 0: Clock 1: Clock 2:
The PCI bus cycle address is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as an access to Pass-Thru region 1. PCI data is stored in the S5935 Pass-Thru Data Register. PTATN# is asserted to indicate a Pass-Thru access is occurring. Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# Deasserted. The access has a single data phase. 01. Indicates the PCI access is to Pass-Thru region 1. Asserted. The Pass-Thru access is a write. 0h. Indicate the Pass-Thru access is 32-bits.
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 3: Clock 4: Clock 5: SELECT#, byte enable, and the address inputs remain valid to read the Pass-Thru Data Register at offset 2Ch. RD# is asserted to drive data register contents onto the DQ bus. If PTRDY# is asserted at the rising edge of clock 4, PTATN# is immediately deasserted and the Pass-Thru access is completed at clock 5. If Add-On logic requires more time to read the Pass-Thru Data Register (slower memory or peripherals), PTRDY# can be delayed, extending the cycle. PTRDY# asserted at the rising edge of clock 5 causes PTATN# to be immediately deasserted. PTATN# and PTBURST# deasserted at the rising edge of clock 6 indicates the Pass-Thru access is complete. The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 7.
Clock 6:
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Single Cycle Pass-Thru Reads
A single cycle Pass-Thru read operation occurs when a PCI initiator reads a single value from a Pass-Thru region. PCI single cycle transfers consists of an address phase and a one data phase. During the address phase of the PCI transfer, the S5935 stores the PCI address into the Pass-Thru Address Register (APTA). If the S5935 determines that the address is
Clock 0: Clock 1:
within one of its defined Pass-Thru regions, it indicates to the Add-On that a write to the Pass-Thru Data Register (APTD) is required. Figure 3 shows a single cycle Pass-Thru read access (Add-On write) using PTADR#. The Add-On reads data from a source on the Add-On and writes it to the APTD register.
PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI cycle is recognized as an access to Pass-Thru region 1. PTATN# is asserted by the S5935 to indicate a Pass-Thru access is occurring. Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 1. PTBURST# PTWR PTBE[3:0]# Deasserted. The access has a single data phase. PTNUM[1:0] 01. Indicates the PCI access was to Pass-Thru region 1. Deasserted. The Pass-Thru access is a read. 0h. Indicate the Pass-Thru access is 32-bits.
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 2: Clock 3: This clock is required to avoid contention on the DQ bus. Time must be allowed after PTADR# is deasserted for the DQ outputs to float before Add-On logic attempts to write to the Pass-Thru Data Register. SELECT#, byte enables, and the address inputs remain valid to write the Pass-Thru Data Register at offset 2Ch. If WR# is asserted at the rising edge of clock 3, data on the DQ bus is latched into APTD. If PTRDY# is asserted at the rising edge of clock 3, PTATN# is immediately deasserted and the Pass-Thru access is completed at clock 4. Clock 4: If Add-On logic requires more time to write the Pass-Thru data register (slower memory or peripherals), PTRDY# can be delayed, extending the cycle. PTRDY# asserted at the rising edge of clock 4 causes PTATN# to be immediately deasserted and the Pass-Thru access is completed at clock 5. PTATN# and PTBURST# deasserted at the rising edge of clock 5 indicates the Pass-Thru access is complete. The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 6.
Clock 5:
Pass-Thru Burst Writes
A Pass-Thru burst write operation occurs when a PCI initiator writes multiple values to a Pass-Thru region. A PCI burst cycle consists of an address phase and multiple data phases. During the address phase of the PCI transfer, the S5935 stores the PCI address into the Pass-Thru Address Register (APTA). If the S5935 determines that the address is within one of its defined Pass-Thru regions, it captures the PCI data into the Pass-Thru Data Register (APTD). After the Add-On completes each read from the Pass-Thru data register (asserts PTRDY#), the next data phase is initiated.
Figure 4 shows a 6 data phase Pass-Thru burst write (Add-On read). In this case, the Add-On asserts PTADR# and then reads multiple data phases from the S5935. This works well for Add-On logic which supports burst cycles. If the Add-On logic does not support burst accesses, PTADR# may be pulsed before each data phase. The S5935 automatically increments the address in the APTA register during PCI burst cycles. In this example PTRDY# is always asserted, indicating Add-On logic is capable of accepting data at a rate of one DWORD per clock cycle.
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Clock 0: Clock 1: PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as an access to Pass-Thru region 1. PCI data for the first data phase is stored in the S5935 Pass-Thru Data Register. PTATN# is asserted by the S5935 to indicate a Pass-Thru access is occurring. Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# Asserted. The access has a multiple data phases. 01. Indicates the PCI access was to Pass-Thru region 1. Asserted. The Pass-Thru access is a write. 0h. Indicate the Pass-Thru access is 32-bits.
Clock 2:
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 3: Clock 4: Clock 5: Clock 6: SELECT#, byte enables, and the address inputs remain driven to read the Pass-Thru Data Register at offset 2Ch. RD# is asserted to drive data register contents onto the DQ bus. Add-On logic uses the rising edge of clock 4 to store DATA 1 from the S5935. PTRDY# asserted at the rising edge of clock 4 completes the current data phase. DATA 2 is driven on the Add-On bus. Add-On logic uses the rising edge of clock 5 to store DATA 2 from the S5935. PTRDY# asserted at the rising edge of clock 5 completes the current data phase. DATA 3 is driven on the Add-On bus. Add-On logic uses the rising edge of clock 6 to store DATA 3 from the S5935. PTRDY# asserted at the rising edge of clock 6 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. This is how a PCI initiator adds wait states, if it cannot provide data quickly enough. Data on the Add-On bus is not valid. Because PTATN# remains deasserted, Add-On logic cannot store data at the rising edge of clock 7. PTATN# is reasserted, indicating the PCI initiator is no longer adding wait states. DATA 4 is driven on the Add-On bus. Add-On logic uses the rising edge of clock 8 to store DATA 4 from the S5935. PTRDY# asserted at the rising edge of clock 8 completes the current data phase. On the PCI bus, IRDY# has been deasserted again, causing PTATN# to be deasserted. Data on the Add-On bus is not valid. The PCI initiator is still adding wait states. Add-On logic cannot store data while PTATN# is deasserted. Because PTATN# remains deasserted, Add-On logic cannot read data at the rising edge of clock 10. PTATN# is reasserted, indicating the PCI initiator is no longer adding wait states. DATA 5 is driven on the Add-On bus. Add-On logic uses the rising edge of clock 11 to store DATA 5 from the S5935. PTRDY# asserted at the rising edge of clock 11 completes the current data phase. DATA 6 is driven on the Add-On bus. Add-On logic uses the rising edge of clock 12 to store DATA 6 from the S5935. PTRDY# asserted at the rising edge of clock 12 completes the final data phase. PTATN# and PTBURST# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete. The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 15.
Clock 7: Clock 8:
Clock 9: Clock 10: Clock 11: Clock 12: Clock 13:
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Figure 82. Single Cycle Pass-Thru Read with PTADR#
012345 BPCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# SELECT# ADR[6:2] BE[3:0]# WR# DQ[31:0] PTRDY# PTADR# Data stored in Pass-Thru data register PCI Read cycle completed PT ADDR PT DATA 2Ch 0h 0h 1 6
Figure 83. Pass-Thru Burst Write
0 BPCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# SELECT# ADR[6:2] BE[3:0]# RD# DQ[31:0] PTRDY# PTADR#
PT ADDRDATA1 DATA2 DATA3 XXXX DATA4 XXXX DATA5 DATA6 XXXX
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Valid PCI data on DQ bus
PCI Burst Write completed
Figure 5 also shows a 5 data phase Pass-Thru burst write, but the Add-On logic uses PTRDY# to control the rate at which data is transferred. In many applications, Add-On logic is not fast enough to accept data at every BPCLK rising edge (every 30 ns in a 33 MHz
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Figure 84. Pass-Thru Burst Writes Controlled by PTRDY#
0 BPCLK PTATN# PTBURST# PTNUM[1:0] 0 PTWR PTBE[3:0]# Fh SELECT# ADR[6:2] BE[3:0]# RD# DQ[31:0] PTRDY# PTADR#
PT ADDR DATA1 DATA2 DATA3 XXXX DATA4 DATA5
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Valid PCI data on DQ bus
PCI Burst Write completed
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Clock 0: Clock 1: PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as an access to Pass-Thru region 1. PCI data for the first data phase is stored in the S5935 Pass-Thru Data Register. PTATN# is asserted by the S5935 to indicate a Pass-Thru access is occurring. Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# Asserted. The access has multiple data phases. 01. Indicates the PCI access is to Pass-Thru region 1. Asserted. The Pass-Thru access is a write. 0h. Indicate the Pass-Thru access is 32-bits. The PTADR# input is asserted to read the Pass-Thru Address Register. The byte en-able, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3.
Clock 2:
Clock 3: Clock 4: Clock 5: Clock 6: Clock 7: Clock 8:
SELECT#, byte enable, and the address inputs remain driven to read the Pass-Thru Data Register at offset 2Ch. RD# is asserted to drive data register contents onto the Add-On data bus. Add-On logic uses the rising edge of clock 4 to store DATA 1 from the S5935. PTRDY# asserted at the rising edge of clock 4 completes the current data phase. DATA 2 is driven on the Add-On bus. Add-On logic is not fast enough to store DATA 2 by the rising edge of clock 5. PTRDY# deasserted at the rising edge of clock 5 extends the current data phase and DATA 2 remains driven on the Add-On bus. Add-On logic uses the rising edge of clock 6 to store DATA 2 from the S5935. PTRDY# asserted at the rising edge of clock 6 completes the current data phase. DATA 3 is driven on the Add-On bus. Add-On logic is not fast enough to store DATA 3 by the rising edge of clock 7. PTRDY# deasserted at the rising edge of clock 7 extends the current data phase is and DATA 3 remains driven on the Add-On bus. Add-On logic uses the rising edge of clock 8 to store DATA 3 from the S5935. PTRDY# asserted at the rising edge of clock 8 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. Data on the Add-On bus is not valid. Because PTATN# remains deasserted, Add-On logic cannot store data at the rising edge of clock 9. PTATN# is reasserted, indicating the PCI initiator is no longer adding wait states. DATA 4 is driven on the Add-On bus. Add-On logic uses the rising edge of clock 10 to store DATA 4 from the S5935. PTRDY# asserted at the rising edge of clock 10 completes the current data phase. DATA 5 is driven on the Add-On bus. PTBURST# is deasserted, indicating that on the PCI bus, the burst is complete except for the last data phase. Since the data is double buffered, there may be one or two pieces of data available to the Add-On when PTBURST# becomes inactive. This example shows the single data available case. If another piece of data was available, then PTATN# would remain active instead of going inactive at clock 12.
Clock 9: Clock 10:
Clock 11: Clock 12: Clock 13:
Add-On logic is not fast enough to store DATA 5 by the rising edge of clock 11. PTRDY# deasserted at the rising edge of clock 11 extends the data phase and DATA 5 remains driven on the Add-On bus. Add-On logic uses the rising edge of clock 12 to store DATA 5 from the S5935. PTRDY# asserted at the rising edge of clock 12 completes the final data phase. PTATN# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete. The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 14.
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Pass-Thru Burst Reads
A Pass-Thru burst read operation occurs when a PCI initiator reads multiple DWORDs from a Pass-Thru region. A burst transfer consists of a single address and a multiple data phases. During the address phase of the PCI transfer, the S5935 stores the PCI address
Figure 85. Pass-Thru Burst Read
0 BPCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# SELECT# ADR[6:2] BE[3:0]# WR# DQ[31:0] PTRDY# PTADR#
PT ADDR DATA1 DATA2 DATA3
into the Pass-Thru Address Register (APTA). If the S5935 determines that the address is within one of its defined Pass-Thru regions, it indicates to the Add-On that a write to the Pass-Thru Data Register (APTD) is required. Figure 6 shows a 6 data phase Pass-Thru burst read access (Add-On write) using PTADR#.
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DATA4
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DATA7
Valid Data written into data register
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Clock 0: PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as an access to Pass-Thru region 1. PTATN# is asserted by the S5935 to indicate a Pass-Thru access is occurring. PTBURST# is asserted by the S5935, indicating the current Pass-Thru read is a burst. Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# Deasserted, the S5935 does not yet recognize a PCI burst. 01. Indicates the PCI access is to Pass-Thru region 1. Deasserted. The Pass-Thru access is a read. 0h. Indicate the Pass-Thru access is 32-bits. The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3.
Clock 1:
Clock 2: Clock 3: Clock 4: Clock 5:
SELECT#, byte enables, and the address inputs remain driven to read the Pass-Thru Data Register at offset 2Ch. WR# asserted at the rising edge of clock 3 writes DATA 1 into the S5935. PTRDY# asserted at the rising edge of clock 3 completes the current data phase. WR# asserted at the rising edge of clock 4 writes DATA 2 into the S5935. PTRDY# asserted at the rising edge of clock 4 completes the current data phase. WR# asserted at the rising edge of clock 5 writes DATA 3 into the S5935. PTRDY# asserted at the rising edge of clock 5 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. This is how a PCI initiator adds wait states, if it cannot read data quickly enough. PTATN# remains deasserted at the rising edge of clock 6. The Add-On cannot write DATA 4 until PTATN# is asserted. PTATN# is reasserted during the cycle, indicating the PCI initiator is no longer adding wait states. Add-On logic continues to drive DATA 4 on the Add-On bus. WR# asserted at the rising edge of clock 7 writes DATA 4 into the S5935. PTRDY# asserted at the rising edge of clock 7 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. The PCI initiator is adding wait states. PTATN# remains deasserted at the rising edge of clock 8. The Add-On cannot write DATA 5 until PTATN# is asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. PTATN# remains deasserted at the rising edge of clock 9. The Add-On cannot write DATA 5 until PTATN# is asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. PTATN# is reasserted during the cycle, indicating the PCI initiator is done adding wait states. WR# asserted at the rising edge of clock 10 writes DATA 5 into the S5935. PTRDY# asserted at the rising edge of clock 10 completes the current data phase. WR# asserted at the rising edge of clock 11 writes DATA 6 into the S5935. PTRDY# asserted at the rising edge of clock 11 completes the final data phase. PTBURST# is deasserted at the rising edge of clock 12 indicating the Pass-Thru burst is complete. The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 14. Any data written into the Pass-Thru data register is not required and is never passed to the PCI interface (as PTRDY# is not asserted at the rising edge of clock 13).
Clock 6:
Clock 7:
Clock 8: Clock 9:
Clock 10: Clock 11: Clock 12:
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Figure 7 also shows a 5 data phase Pass-Thru burst read, but the Add-On logic uses PTRDY# to control the rate at which data is transferred. In many applications, Add-On logic is not fast enough to provide data every BPCLK (every 30 ns in a 33 MHz PCI system).
Figure 86. PCI Burst Read Controlled by PTRDY#
0 BPCLK PTATN# PTBURST# PTNUM[1:0] 0 PTWR PTBE[3:0]# Fh SELECT# ADR[6:2] BE[3:0]# WR# DQ[31:0] PTRDY# PTADR#
PT ADDR DATA1 DATA2 DATA3 DATA4 DATA5
In this example, the Add-On interface writes data every other clock cycle. WR# is shown asserted during the entire Add-On burst, but WR# can be deasserted when PTRDY# is deasserted, the S5935 functions the same under both conditions.
1
2
3
4
5
6
7
8
9
10
11
12
13
1
0h
2Ch 0h
Valid data written into data register
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Clock 0: PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as an access to Pass-Thru region 1. PTATN# is asserted by the S5935 to indicate a Pass-Thru access is occurring. PTBURST# is asserted by the S5935, indicating the current Pass-Thru read is a burst. Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# PTNUM[1:0] 01. PTWR PTBE[3:0]# Deasserted, the S5935 does not yet recognize a PCI burst. Indicates the PCI access is to Pass-Thru region 1. Deasserted. The Pass-Thru access is a read. 0h. Indicate the Pass-Thru access is 32-bits.
Clock 1:
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 2: Clock 3: Clock 4: Clock 5: Clock 6: Clock 7: SELECT#, byte enable, and the address inputs remain driven to read the Pass-Thru Data Register at offset 2Ch. WR# asserted at the rising edge of clock 3 writes DATA 1 into the S5935. PTRDY# asserted at the rising edge of clock 3 completes the current data phase. Add-On logic drives DATA 2 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 4 extends the current data phase. WR# asserted at the rising edge of clock 5 writes DATA 2 into the S5935. PTRDY# asserted at the rising edge of clock 5 completes the current data phase. Add-On logic drives DATA 3 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 6 extends the current data phase. WR# asserted at the rising edge of clock 7 writes DATA 3 into the S5935. PTRDY# asserted at the rising edge of clock 7 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. This is how a PCI initiator adds wait states, if it cannot read data quickly enough. PTATN# remains deasserted at the rising edge of clock 8. The Add-On cannot write DATA 4 until PTATN# is asserted. Add-On logic continues to drive DATA 4 on the Add-On bus. PTATN# is reasserted during the cycle, indicating the PCI initiator is done adding wait states. WR# asserted at the rising edge of clock 9 writes DATA 4 into the S5935. PTRDY# asserted at the rising edge of clock 9 completes the current data phase. Add-On logic drives DATA 5 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 10 extends the current data phase. PTATN# remains deasserted at the rising edge of clock 11. The Add-On does not have to write DATA 5 until PTATN# is asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. PTATN# is reasserted during the cycle, indicating the PCI initiator is done adding wait states. PTRDY# asserted at the rising edge of clock 12 completes the final data phase. Any data written into the PassThru data register is not required and is never passed to the PCI interface (as PTRDY# is not asserted at the rising edge of clock 13). PTATN# and PTBURST# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete. The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 14.
Clock 8:
Clock 9: Clock 10: Clock 11:
Clock 12:
Clock 13:
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Add-On Pass-Thru Disconnect Operation
Slow PCI targets are prevented from degrading PCI bus performance. The PCI specification allows only 16 clocks for a target to respond before it must request a retry on single data phase accesses. For burst accesses, the first data phase is allowed 16 clocks to complete, all subsequent data phases are allowed 8 clocks each. This requirement allows other PCI initiators to use the bus while the target requesting the retry completes the original access. Figure 8 shows the conditions that cause the S5935 to request a retry from a PCI initiator on the first data
phase of a PCI read operation. FRAME# is asserted during the rising edge of PCI clock 1. From this point, the S5935 has 16 clock cycles to respond to the initiator with TRDY# (completing the cycle). FRAME# could remain asserted, indicating a burst read, but the retry request conditions are identical for a single data phase read and the first data phase of a burst read. BPCLK is identical to PCICLK, lagging by a propagation delay of a few nanoseconds (see Chapter 13). PTATN# is asserted on the Add-On interface as soon as FRAME# is sampled active at a PCICLK rising edge.
Figure 87. Target Requested Retry on the First PCI Data Phase
1 PCICLK FRAME# STOP# 1 BPCLK PTATN# PTRDY# PTRDY# must be asserted by this time to present disconnecting PTRDY# asserted too late so S593X disconnects (asserts STOP#) 2 3 14 15 16 17 2 3 4 15 16 17 18
After PTATN# is asserted, PTRDY# must be asserted by the 15th BPCLK rising edge to prevent the S5935 from requesting a retry. TRDY# is asserted on the PCI interface one clock cycle after PTRDY# is asserted on the Add-On interface. If Add-On logic does not return PTRDY# by the 15th BPCLK rising edge, the S5935 asserts STOP#, requesting a retry from the PCI initiator. For Pass-Thru write operations, the S5935 never disconnects on the first or second PCI data phases of a
burst. The first data and second phases are always accepted immediately by the S5935. No further action is required by the PCI initiator. The only situation where the S5935 may respond to a Pass-Thru write with a retry request is after the second data phase of a Pass-Thru burst write. Figure 9 shows the conditions required for the S5935 to request a retry after the second data phase of a burst transfer. This figure applies to both Pass-Thru burst read and write operations.
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Figure 88. Target Requested Retry after the First Data Phase of a Burst Operation
1 PCICLK FRAME# STOP# 0 BPCLK PTATN# PTRDY# PCI Data Transfer Latest assertion of PTRDY# to prevent disconnect PTRDY# asserted too late, results in disconnect 1 2 7 8 9 6 7 8
The previous data phase is completed with the assertion of PTRDY# at the rising edge of BPCLK 0. AddOn logic must assert PTRDY# by the rising edge of BPCLK 8 to prevent the S5935 from asserting STOP#, requesting a retry. Meeting this condition allows the S5935 to assert TRDY# by the rising edge of PCICLK 8, completing the data phase with requiring a retry. When the S5935 requests a retry, the Pass-Thru status indicators remain valid (allowing the Add-On logic to complete the access). PTBURST# is the exception to this. PTBURST# is deasserted to indicate that there is currently no burst in progress on the PCI bus. The other Pass-Thru status indicators remain valid until PTATN# is deasserted. Figure 10 shows the Add-On bus interface signals after the S5935 requests a retry. As long as PTATN# remains asserted, Add-On logic should continue to transfer data. For PCI read operations, one Add-On write operation is required after a retry request. After the Add-On write, asserting PTRDY# deasserts PTATN#. For Pass-Thru write operations, one or two data transfers may remain after the S5935 signals a retry. Two
data transfers are possible because the S5935 has a double buffered Pass-Thru data register used for writes. A PCI burst may have filled both registers before the S5935 requested a retry. PTATN# remains asserted until both are emptied. PTRDY# must be asserted after each read from the Pass-Thru data register. If both registers are full, PTATN# is deasserted only after PTRDY# is asserted the second time. The S5935 only accepts further PCI accesses after both registers are emptied.
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface
The S5935 allows a simple interface to devices with 8bit or 16-bit data buses. Each Pass-Thru region may be defined as 8-, 16-, or 32-bits, depending on the contents of the nv memory boot device loaded into the PCI Base Address Configuration Registers during initialization. The Pass-Thru Add-On interface internally controls byte lane steering to allow access to the 32bit Pass-Thru Data Register (APTD) from 8-bit or 16bit Add-On buses.
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Figure 89. Pass-Thru Signals after a Target Requested Retry
STOP# BPCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# SELECT# ADR[6:2] BE[3:0]# RD# DQ[31:0] PTRDY# Data 2Ch 0h 0h Fh 1
Internal byte lane steering may be used whether the MODE input defines a 16-bit or 32-bit Add-On interface. When a 16-bit Add-On interface is used, the ADR1 input is used in conjunction with the byte enables to steer data into the proper APTD register byte locations. If MODE defines a 16-bit interface, only 16-bits of address are driven when PTADR# is asserted. If more than 16-bits of address are required, the Pass-Thru A d d r e s s R e g i s t e r ( A PTA ) m u s t b e r e a d w i t h SELECT#, RD#, byte enable and address inputs. Two consecutive reads are required to latch all of the address information (one with ADR1=0, one with ADR1=1). Regardless of MODE, various data widths may be used. For Pass-Thru writes (Add-On APTD reads), Add-On logic must read the APTD register one byte or one word at a time (depending on the Add-On bus width). The internal data bus is steered to the correct portion of APTD using the BE[3:0]# inputs. Table 1 shows the byte lane steering mechanism used by the S5935. The BYTEn symbols indicate data bytes in the Pass-Thru Data Register. When a read is performed with a BEn# input asserted, the corresponding PTBEn# output is deasserted. Add-
On logic cycles through the byte enables to read the e n t i r e A P T D r e g i s t e r. O n c e a l l d a t a i s r e a d (PTBE[3:0]# are deasserted), PTRDY# is asserted by the Add-On, completing the access. For Pass-Thru reads (Add-On APTD writes), the bytes requested by the PCI initiator are indicated by the PTBE[3:0]# outputs. Add-On logic uses the PTBE[3:0]# signals to determine which bytes must be written (and which bytes have already been written). For example, a PCI initiator performs a byte Pass-Thru read from an 8-bit Pass-Thru region with PCI BE2# asserted. On the Add-On interface, PTBE2# is asserted, indicating that the PCI initiator requires data in this byte. Once the Add-On writes APTD, byte 2, PTBE2# is deasserted, and the Add-On may assert PTRDY#, completing the cycle. Table 2 shows how the external Add-On data bus is steered to the Pass-Thru Data Register bytes. This mechanism is determined by the Pass-Thru region bus width defined during initialization (see Section 12.3). The BYTEn symbols indicate data bytes in the Pass-Thru Data Register. For example, an 8-bit AddOn write with BE1# asserted results in the data on DQ[7:0] being steered into BYTE1 of the APTD register.
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Table 44. Byte Lane Steering for Pass-Thru Data Register Read (PCI Write)
Byte Enables 3 x x x 0 2 x x 0 1 1 x 0 1 1 0 0 1 1 1 DQ[31:24] BYTE3 BYTE3 BYTE3 BYTE3 APTD Register Read Byte Lane Steering DQ[23:16] BYTE2 BYTE2 BYTE2 BYTE3 DQ[15:8] BYTE1 BYTE1 BYTE3 BYTE3 DQ[7:0] BYTE0 BYTE1 BYTE2 BYTE3
Table 45. Byte Lane Steering for Pass-Thru Data Register Write (PCI Read)
Defined PT-Bus Width 32-Bit Data Bus 16-Bit Data Bus 8-Bit Data Bus APTD Register Write Byte Lane Steering BYTE3 DQ[31:24] DQ[15:8] DQ[7:0] BYTE2 DQ[23:16] DQ[7:0] DQ[7:0] BYTE1 DQ[15:8] DQ[15:8] DQ[7:0] BYTE0 DQ[7:0] DQ[7:0] DQ[7:0]
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To write data into the APTD Register, the PTBEn# output and the BEn# input must both be asserted. The following describes how APTD Register writes are controlled: Write BYTE3 if PTBE3# AND BE3# are asserted Write BYTE2 if PTBE2# AND BE2# are asserted Write BYTE1 if PTBE1# AND BE1# are asserted Write BYTE0 if PTBE0# AND BE0# are asserted After each byte is written into the Pass-Thru data regi s t e r, i ts c or re s po nd i ng PTB E [ 3: 0 ] # o ut pu t i s deasserted. This allows Add-On logic to monitor which bytes have been written, and which bytes remain to be written. When all bytes requested by the PCI initiator have been written, the PTBE[3:0]# are all be deasserted, and the Add-On asserts PTRDY#. Figure 11 shows Pass-Thru operation for a region defined for an 8-bit Add-On bus interface. As the 8-bit device is connected only to DQ[7:0], the device must access APTD one byte at a time. The PCI initiator has performed a 32-bit write of 08D49A30h to Pass-Thru region zero. PTBE[3:0]# are all asserted. At clock 1, the Add-On begins reading the APTD Register (asserting SELECT#, ADR[6:2], and RD#). Add-On logic asserts BE0#, and BYTE0 of APTD is driven on DQ[7:0]. At the rising edge of clock 2, BE0# is sampled by the S5935 and PTBE0# is deasserted. PTBE[3:1]# are still asserted. During clock 2, only BE1# is activated, and BYTE1 of APTD is driven on DQ[7:0]. At the rising edge of clock 3, BE1# is sampled by the S5935 and PTBE1# is deasserted. PTBE[3:2]# are still asserted.
Figure 90. Pass-Thru Write to an 8-bit Add-On Device
1 BPCLK PTATN# PTWR PTBE[3:0]# PTNUM[1:0] PTBURST# SELECT# BE[3:0]# ADR[6:2] RD# DQ[7:0] PTADR# PTRDY#
ADDR 30h 9Ah D4h 08h DDh CCh BBh AAh Fh 3Ch Eh Dh Bh 7h Fh 2Ch Eh Dh Bh 7h Fh 3Ch Fh 0h 0 1h 3h 7h Fh 0h 1h 3h 7h Fh
This process continues until all bytes have been read from the APTD Register. During clock 5, RD# is deasserted and PTRDY# is asserted. PTRDY# is sampled by the S5935 at the rising edge of clock 6, and the current data phase is completed. PTATN# is deasserted and new data can be written from the PCI bus. In this example, the byte enables are asserted, sequentially, from BE0# to BE3#. This is not required, bytes may be accessed in any order. New data is written by the PCI initiator and is available in the APTD Register during clock 7. RD# is asserted and the byte enables are cycled again. With each new data from the PCI bus, the Add-On sequences through the byte enables to access APTD via DQ[7:0]. For 16-bit peripheral devices, the byte steering works in the same way. Because the Add-On data bus is 16bits wide, only two 16-bit cycles are required to access the entire APTD Register. Two byte enables can be asserted during each access. In Figure 11, RD# is held low and the byte enables are changed each clock. This assumes the Add-On can accept data at one byte per clock. This is the fastest transfer possible. For slower devices, wait states may be added. As long as the byte enables remain in a given state, the corresponding byte of the APTD Register is connected to the DQ bus (the RD# or WR# pulse may also be lengthened). Each access may be extended for slower Add-On devices, but extending individual data phases for Pass-Thru cycles may result in the S5935 requesting retries by the initiator.
2
3
4
5
6
7
8
9
10
11
12
13
Note: 8 Bit Mode BE's are E, D, B, 7; 16 Bit Mode BE's are C, 3.
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CONFIGURATION
The S5935 Pass-Thru interface utilizes four Base Address Registers (BADR1:4). Each Base Address Register corresponds to a Pass-Thru region. The contents of these registers during initialization determine the characteristics of that particular Pass-Thru region. Each region can be mapped to memory or I/O space. Memory mapped devices can, optionally, be mapped below 1 Mbyte and can be identified as prefetchable. Both memory and I/O regions can be configured as 8-, 16-, or 32-bits wide. The designer has the option to use 1, 2, 3, 4 or none of the Pass-Thru regions. Base Address Registers are loaded during initialization from the external non-volatile boot device. Without an external boot device, the default value for the BADR registers is zero (region disabled). The Base Address Registers are the only registers that define Pass-Thru operation.
S5935 Base Address Register Definition
D31 0 0 1 1 D30 0 1 0 1 Add-On Bus Width Region disabled 8-bits 16-bits 32-bits
BADR1:4 bits D31:30 are used only by the S5935. When the host reads the Base Address Registers during configuration cycles, they always return the same value as D29. If D29 is zero, D31:30 return zero, indicating the region is disabled. If D29 is one, D31:30 return one. This operation limits each Pass-Thru region to a maximum size of 512 Mbytes of memory. For I/O mapped regions, the PCI specification allows no more than 256 bytes per region. The S5935 allows larger regions to be requested by the Add-On, but a PCI BIOS will not allocate the I/O space and will probably disable the region.
Creating a Pass-Thru Region
Some bits in the Base Address Registers have specific functions. The following bits have special functions:
D0 Memory or I/O mapping. If this bit is clear, the region should be memory mapped. If this bit is set, the region should be I/O mapped. Location of a memory region. These bits request that the region be mapped in a particular part of memory. These bit definitions are only used for memory mapped regions. Prefetchable. For memory mapped regions, the region can be defined as cacheable. If set, the region is cacheable. If this bit is clear, the region is not. Pass-Thru region bus width. These two bits are used by the S5935 to define the data bus width for a Pass-Thru region. Regardless of the programming of other bits in the BADR register, if D31:30 are zeros, the Pass-Thru region is disabled.
D2:1
Page 3-40 describes the values that must be programmed into the non-volatile boot device to request various block sizes and characteristics for Pass-Thru regions. After reset, the S5935 downloads the contents of the boot device locations 54h, 58h, 5Ch, and 60h into "masks" for the corresponding Base Address Registers. The following are some examples for various Pass-Thru region definitions:
D3
NV Memory Contents 54h = BFFFF002h
Pass-Thru Region Definition Pass-Thru region 1 is a 4Kbyte region, mapped below 1 Mbyte in memory space with a 16-bit Add-On data bus. This memory region is not cacheable. Pass-Thru region 2 is disabled. (D31:30 = 00.) Pass-Thru region 3 is a 32-bit, 128 byte I/O-mapped region. Pass-Thru region 4 is disabled.
D31:30
58h = 3xxxxxxxh 60h = FFFFFF81h 64h = 00000000h
D2 0 0 1 1
D1 0 1 0 1
Location Anywhere in 32-bit memory space Below 1 Mbyte in memory space (Real Mode address space) Anywhere in 64-bit memory space (not valid for the S5935) Reserved
During the PCI bus configuration, the host CPU writes all ones to each Base Address Register, and then reads the contents of the registers back. The mask downloaded from the boot device determines which bits are read back as zeros and which are read back
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as ones. The number of zeros read back indicates the amount of memory or I/O space a particular S5935 Pass-Thru region is requesting. After the host reads all Base Address Registers in the system (as every PCI device implements from one to six), the PCI BIOS allocates memory and I/O space to each Base Address region. The host then writes the start address of each region back into the Base Address Registers. The start address of a region is always an integer multiple of the region size. For example, a 64 Kbyte memory region is always mapped to begin on a 64K boundary in memory. It is important to note that no PCI device can xbe absolutely located in system memory or I/O space. All mapping is determined by the system, not the application.
Accessing a Pass-Thru Region
particular devices on the PCI bus based on Vendor ID and Device ID values. This allows application software to access the device's Configuration Registers. The Base Address Register values in the S5935's Configuration Space may then be read and stored for use by the program to access application hardware. The value in the Base Address Registers is the physical address of the first location of that Pass-Thru region. Some processor architectures allow this address to be used directly to access the PCI device. For Intel Architecture systems, the physical address must be changed into a Segment/Offset combination. For Real Mode operation in an Intel Architecture system (device mapped below 1 Mbyte in memory), creating a Segment/Offset pair is relatively simple. To calculate a physical address, the CPU shifts the segment register 4 bits to the left and adds the offset (resulting in a 20 bit physical address). The value in the Base Address Register must be read and shifted 4 bits to the right. This is the segment value and should be stored in one of the Segment registers. An offset of zero (stored in SI, DI or another offset register) accesses the first location in the Pass-Thru region.
After the system is finished defining all Base Address Regions within a system, each Base Address Register contains a physical address. The application software must now find the location in memory or I/O space of its hardware. PCI systems provide BIOS or operating system function calls for application software to find
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ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Supply Voltage (VCC) Input Pin Voltage Power Dissipation Min Max Units
-55 -0.3 -0.5
125 7.0 VCC+ 5.0 1.05
C Volts Volts Watts @ 33 MHz
DC CHARACTERISTICS
The Following table summarizes the required parameters defined by the PCI specification as they apply to the S5935 controller. PCI Input/Output Electrical Characteristics
Symbol VCC VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL
Notes: 1. Input leakage applies to all inputs and bi-directional buffers. 2. PCI Bus signals without pull-up resistors will provide the 3 mA output current. Signals which require a pull-up resistor will provide 6 mA output current. 3. The PCI specification limits all PCI inputs not located on the motherboard to 10 pf (the clock is allowed to be 12 pf).
Parameter Supply Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capaticance
Min 4.75 2.0 -0.5
Max 5.25
Units V V
Test Conditions
Notes
0.8 70 -70
V uA uA V VIN = 2.7 VIN = 0.5 IOUT = -2mA IOUT = 3mA, 6mA V in = 0.5 2 3 1 1
2.4 0.55 10 5 12 8
V pF pF pF
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PCI BUS SIGNALS
The following table summarizes the PCI Bus DC parameters defined by the PCI specification as they apply to the S5935 controller.
Signal CLK RST# INTA#
Type Input Input Open Drain Output
Direction
Max
Units
Notes
4
mA
AD[31:0]
t/s
Bi-directional
mA
REQ# GNT# C/BE[3:0]# DEVSEL#
t/s
Output Input
4
mA
t/s s/t/s
Bi-directional Bi-directional
4
mA mA
FRAME# IRDY# TRDY#
s/t/s s/t/s s/t/s
Bi-directional Bi-directional Bi-directional
4 4 4
mA mA mA
PERR# PAR SERR#
s/t/s t/s Open Drain
Bi-directional Bi-directional Output
4 4 4
mA mA mA
STOP# LOCK# IDSEL
s/t/s
Bi-directional Input Input
4
mA
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ADD-ON BUS SIGNALS
Signal PCLK IRQ# SYSRST# Type Output Output Output Direction Max 8 4 4 Units mA mA mA Notes
ADR[6:2] SELECT ADR[6:2] BE[3:0]# RD# WR# DQ[31:0] WRFULL RDEMPTY RDFIFO# WRFIFO# t/s
Input Input Input Input Input Input Bi-directional Output Output Input Input 4 4 4 mA mA mA
PTATN# PTBURST# PTADR# PTRDY# PTWR PTBE[3:0]# PTNUM[1:0]
Output Output Input Input Output Output Output
4 4
mA mA
4 4 4
mA mA mA
EQ[7:0] EA[8:0] EA[15:9]
t/s t/s
Bi-directional Output Output
1 1 1
mA mA mA
MODE TEST FLT#
Input Output Input 4 mA
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Signal ERD#/SCL EWR#/SDA t/s Type Output Bi-directional Direction Max 1 1 Units mA mA Notes
AC CHARACTERISTICS
PCI Bus Timings
Functional Operation Range (V CC =5.0V 5%, 0C to 70C, 50 pF load on outputs)
Symbol TCL t1 t2 t3 t4 t5 t6 t7 t8 Cycle Time High Time Low Time Rise Time (0.8V to 2.0V) Fall Time (2.0V to 0.8V) Output Valid Delay (Bussed Signals) Output Valid Delay (Point-to-Point Signals) Float to Active Delay Active to Float Delay Rising Edge Setup (Bussed Signals) Rising Edge Setup (GNT#) Rising Edge Setup (REQ#) Hold from PCI Clock Rising Edge PCICLK to BPCLK Delay 2 2 2 28 7 10 12 0 2 6.5 ns ns Parameter Min 30 12 12 3 3 11 12 Max Units ns ns ns ns ns ns ns Note 1 Notes
t9 t10
Note:
ns ns
1. Minimum times are for unloaded outputs, maximum times are for 50 pF equivalent loads.
Figure 91. PCI Clock Timing
t1 2.0 VIH2 2.0 0.8 t2
t3
t4
2.0 0.8 TCL
2.0 0.8
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Figure 92. PCI Output Timing
PCI CLK
1.5
t5
OUTPUT DELAY
1.5
TRI-STATE OUTPUT
1.5
1.5
t6 t7
Figure 93. PCI Input Timing
PCI CLK
t8
INPUT
t9
Inputs Valid
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ADD-ON BUS TIMINGS
Figure 94. Add-On Clock Timing
t1
2.0 2.0 0.8
t3 V IH2 t2 TCL
2.0 0.8 2.0 0.8
t4
Figure 95. Pass-Thru Clock Relationship to PCI Clock
PCI CLK
t10
BPCLK
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Synchronous RDFIFO# Timing
Functional Operation Range (VCC=5.0V 5%, 0 C to 70 C Ta' 50 pf loaf on outputs).
Symbol t144 t145 t146 t148 t149 t165 t166
Notes: 1. Min and Max times are indicated to allow increased valid data time as shown by dashed lines. 2. 2.State change of RDEMPTY shown below is reference only. Actual change would indicate no Data 3 available. 3. 3.Valid applies after first access. First access is async with following as sync accesses.
Parameter RDFIFO# Setup tp BPCLK Rising Edge RDFIFO# Low Time RDFIFO# Low to DQ[31:0] Driven RDFIFO# High to DQ[31:0] Float DQ[31:0] Valid from BPCLK Rising Edge PCI to ADD-ON FIFO RDEMPTY Valid from BPCLK Rising Edge PCI to ADD-ON FIFO FRF Valid from BPCLK Rising Edge
Min 8 8
Max 26
Units ns ns
Notes 1
12 3 16 12 80
ns ns ns ns ns 3 2
Figure 96. Synchronous RDFIFO# Timing
BPCLK
t 144 Max t 144 t 149
RDFIFO#
t146 10ns 1 14ns 23 t 165 8ns 6ns 4 t148
DQ[31:0]
RDEMPTY
New Valid Old Valid t 166
FRF
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Synchronous WRFIFO# Timing
Functional Operation Range (VCC= 5.0V 5%, 0 C to 70 C Ta' 50 pf load on outputs).
Symbol t150 t150a t151 t151a t167 t168
Note: 1. State change of WRFULL shown below is reference only. Actual change would indicate no Data 3 written.
Parameter WRFIFO# Setup to BPCLK Rising Edge WRFIFO# Hold Time to BPCLK Rising Edge DQ[31:0] Setup to BPCLK Rising Edge DQ[31:0] Hold from BPCLK Rising Edge ADD-ON to PCI WRFULL Valid from BPCLK Rising Edge ADD-ON to PCI FIFO FWE Valid from BPCLK Rising Edge
Min 12 0 7
Max
Units ns ns
Notes
0 11 26 ns ns 1
Figure 97. Synchronous WRFIFO# Timing
BPCLK
t150
t 150a
WRFIFO#
t 151
DQ[31:0]
1
2 t 167 6ns
3
WRFULL
Old Valid t 168
New Valid
FWE
180
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Asynchronous RD# Register Access Timing
Functional Operation Range (VCC=5.0V 5%, 0 C to 70 C Ta' 50 pf load on outputs).
Symbol t110 t114a t114 t114a t118 t118a t129 t130 t133 t133a t152 t153 Parameter SELECT# Setup to RD# Rising Edge SELECT# Hold from RD# Rising Edge ADR[6:2] Setup to RD# Rising Edge ADR[6:2] Hold from RD# Rising Edge BE[3:0]# Setup to RD# Rising Edge BE[3:0]# Hold from RD# Rising Edge RD# High Time RD# Low Time DQ[31:0] Valid from RD# Falling Edge DQ[31:0] Hold from RD# Rising Edge RDEMPTY Status Valid from RD# Rising Edge FRF Status Valid from RD# Rising Edge Min 10 -1 18 0 12 0 16 15 15 3 10 75 ns ns ns ns ns ns ns ns Max Units ns ns ns Notes
Figure 98. Asynchronous RD# FIFO Timing
t 110
SELECT#
t114
ADR[6:2]
t 118
BE[3:0]#
t 133 t133a
DQ[31:0]
t 129 t 130
RD#
t152 5ns
RDEMPTY
T153
FRF
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Asynchronous WR# Register Access Timing
Functional Operation Range (VCC=5.0V 5%, 0 C to 70 C T 50 pf load on outputs).
Symbol t111 t111a t115 t115a t119 t119a t131 t132 t134 t134a t154 t155 Parameter SELECT# Setup to WR# Rising Edge SELECT# Hold from WR# Rising Edge ADR[6:2] Setup to WR# Rising Edge ADR[6:2] Hold from WR# Rising Edge BE[3:0]# Setup to WR# Rising Edge BE[3:0]# Hold from WR# Rising Edge WR# High Time WR# Low Time DQ[31:0] Setup to WR# Rising Edge DQ[31:0] Hold from WR# Rising Edge WRFULL Status Valid from WR# Rising Edge FWE Status Valid from WR# Rising Edge Min 7 0 8 0 5 0 TBD 4 2 3 27 40 Max Units ns ns ns ns ns ns ns ns ns ns ns ns Notes
Figure 99. Asynchronous WR# FIFO Timing
t 111
SELECT#
t 115
ADR[6:2]
t119
BE[3:0]#
t132a t134
DQ[31:0]
t 132
WR#
t154 13ns
WRFULL
t 155
FWE
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Data Book
Synchronous RD# FIFO Timing
Functional Operation Range (VCC=5.0V 5%, 0 C to 70 C T 50 pf load on outputs).
Symbol t112 t112a t116 t116a t120 t120a t125 t128 t156 t157 t124 t124a t127
Notes: 1. Data is valid for 22ns for a 31ns t124 RD# Setup. 2. RD# and SELECT# must both be asserted to dric=ve DQ[31:0] - delay is from the last one asserted. 3. When increasing Setup times, ADR[6:2], BE[3:0]#, SELECT#, and RD# timing relations remain relative to each other as shown. 4. Min and Max are indicated to allow increased valid data time as shown by dashed lines. First accesses are async.
Parameter SELECT# Setup to BPCLK Rising Edge SELECT# Hold from BPCLK Rising Edge ADR[6:2] Setup to BPCLK Rising Edge ADR[6:2] Hold from BPCLK Rising Edge BE[3:0]# Setup to BPCLK Rising Edge BE[3:0]# Hold from BPCLK Rising Edge RD# Low to DQ[31:0] Driven RD# High to DQ[31:0] Float RDEMPTY Status Valid to BPCLK Rising Edge FRF Status Valid to BPCLK Rising Edge RD# Setup to BPCLK Rising Edge RD# Hold from BPCLK Rising Edge DQ[31:0] Valid from BPCLK Rising Edge
Min 10 2 14 1 9 3
Max 30
Units ns ns
Notes 4
34
ns ns
4
29
ns ns
4
17 8 13 74 11 1 6 31
ns ns ns ns ns ns ns
1
4
Figure 100. Synchronous RD# FIFO Timing
BPCLK
t 112 Max t 112 t 112a
SELECT#
t116 t 116a
ADR[6:2]
t120 t120a
BE[3:0]#
t 125
DQ[31:0]
t 124 t128 t 124a t 156 5ns
RD#
RDEMPTY
t157
FRF
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Synchronous Multiple RD# FIFO Timing Figure 101. Synchronous RD# FIFO Timing
t112a
t120a
t116a
t124a
t156
5ns
5ns
3
4
5
6
7
8
11ns
2
t112
t120
t125
t116
t124
2ns
t157 DQ[31:0] RDEMPTY RD# FRF
SELECT#
ADR[6:2]
BPCLK
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Synchronous WR# FIFO Timing
Functional Operation Range (VCC=5.0V 5%, 0 C to 70 C Ta' 50 pf load on outputs).
Symbol t113 t113a t117 t117a t121 t121a t123 t123a t122 t122a t159 t160 Parameter SELECT# Setup to BPCLK Rising Edge SELECT# Hold from BPCLK Rising Edge ADR[6:2] Setup to BPCLK Rising Edge ADR[6:2] Hold from BPCLK Rising Edge BE[3:0]# Setup to BPCLK Rising Edge BE[3:0]# Hold from BPCLK Rising Edge DQ[31:0] Setup to BPCLK Rising Edge DQ[31:0] Hold from BPCLK Rising Edge WR# Setup to BPCLK Rising Edge WR# Hold from BPCLK Rising Edge WRFULL Status Valid to BPCLK Rising Edge FWE Status Valid to BPCLK Rising Edge Min 19 0 20 0 15 0 12 1 20 0 18 26 Max Units ns ns ns ns ns ns ns ns ns ns ns ns Notes
Figure 102. Synchronous WR# FIFO Timing
BPCLK
t 113
SELECT#
t117
ADR[6:2]
t 121
BE[3:0]#
t123 t 123a
DQ[31:0]
t122
WR#
t 159 3ns
WRFULL
t160 4ns
FWE
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Synchronous Multiple WR# FIFO Timing Figure 103. Synchronous Multiple WR# FIFO Timing
t123a
t 159
2 3 4 5 6 7
3ns
t 123
8
t 123
t123a
t 113
t 121
SELECT#
t 117
BE[3:0]#
t 122
186
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WRFULL
ADR[6:2]
DQ[31:0]
BPCLK
WR#
4ns
1
t160
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Data Book
Target S5935 Pass-Thru Interface Timings
Functional Operation Range (VCC=5.0V 5%, 0 C to 70 C, 50 pF load on outputs)
Symbol t10a t11a t12 t13 t14 t17 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34
Note: 1. This timing also applies to the use of BE[3:0]# to control DQ[31:0] drive.
Parameter SELECT# Setup to BPCLK Rising Edge SELECT# Hold from BPCLK Rising Edge ADR[6:2], BE[3:0]# to Valid DQ [31:0] ADR[6:2], BE[3:0]# Setup to BPCLK Rising Edge ADR[6:2], BE[3:0]# Hold from BPCLK Rising Edge RD# Low to DQ{31:0] Driven Pass-Thru Status Valid from BPCLK Rising Edge Pass-Thru Status Hold from BPCLK Rising Edge PTRDY# Setup to BPCLK Rising Edge PTRDY# Hold from BPCLK Rising Edge PCICLK to BPCLK delay RD#, WR# Setup to BPCLK Rising Edge RD#, WR# Hold from BPCLK Rising Edge DQ[31:0] Setup to BPCLK Rising Edge DQ[31:0] Hold from BPCLK Rising Edge DQ[31:0] Valid from BPCLK Rising Edge DQ[31:0] Float from RD# Rising Edge
Min 3 2
Max
Units ns ns
Notes
16 5 2 13 5 0 5 3 2 5 2 5 2 15 12 6.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1
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Figure 104. Pass-Thru Data Register Read Timing
BPCLK t13 ADR[6:2] BE[3:0]# t17 DQ[31:0] t12 t29 Valid Data Out 1 t30 t34 SELECT# t11a PTRDY# t26 t27 Valid 1 t14 Valid 2 t33 Valid Data Out 2
RD#
Figure 105. Pass-Thru Data Register Write Timing
BPCLK t13 ADR[6:2] BE[3:0]# t31 DQ[31:0] Valid 1 t32 Valid Data In 2 t30 t14 Valid 2
Valid Data In 1 t29
WR#
SELECT# t10a PTRDY# t26 t27 t11a
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Figure 106. Pass-Thru Status Indicator Timing
BPCLK PTATN# PTWR PTBURST# PTNUM[1:0] PTBE[3:0]#
Valid t24
Valid t25
Target Byte-Wide nv Memory Interface Timings
Functional Operation Range (V CC =5.0V 5%, 0C to 70C, 50 pF load on outputs)
Symbol t35 t36 t37 t38 t39 t40 t41 t42 t43 t44 t45 t46
Notes: 1. T represents the clock period for the PCI bus clock (30ns @ 33 MHz). 2. The write cycle time is controlled by both the PCI bus clock and software operations to initiate the write operation of nv memory. This parameter is the result of several software operations to the Bus Master Control/Status Register (MCSR).
Parameter ERD# Cycle Time ERD# Low Time ERD# High Time EA[15:0] Setup to ERD# or EWR# Low EA[15:0] Hold from ERD# or EWR# High EQ[7:0] Setup to ERD# Rising Edge EQ[7:0] Hold from ERD# Rising Edge EWR# Cycle Time EWR# Low Time EWR# High Time EQ[7:0] Setup to EWR# Low -10 EQ[7:0] Hold from EWR# High
Min 8T 6T 2T T T 10 2
Max
Units ns ns ns ns ns ns ns ns
Notes Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1,2 Note 1 Note 1 Note 1 Note 1
6T 2T 0 T
ns ns ns ns
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Figure 107. nv Memory Read Timing
t35
ERD#
(OUTPUT)
t37 t38 t36
Address Valid
t39
EA[15:0]
(OUTPUT)
t40
EQ[7:0]
(INPUT)
t41
Data Valid
Figure 108. nv Memory Write Timing
t42 t43
EWR#
(OUTPUT)
t44 t39
Address Valid
t38
EA[15:0]
(OUTPUT)
t45
EQ[7:0]
(OUTPUT)
t46
Data Valid
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Target Interrupt Timings
Functional Operation Range (V CC =5.0V 5%, 0C to 70C, 50 pF load on outputs)
Symbol t49 t50 Parameter IRQ# Low from BPCLK Rising Edge IRQ# High from BPCLK Rising Edge Min Max 15 15 Units ns ns Notes Note 1 Note 1
Notes: 1. This timing applies to interrupts generated and cleared from the PCI interface.
Figure 109. IRQ# Interrupt Output Timing
BPCLK IRQ# t49 t50
Functional Operation Range (V CC =5.0V 5%, 0C to 70C, 50 pF load on outputs)
Symbol t51 t52 t53 t54 EMBCLK Low Time EMBLK High Time EMB[7:0] Setup to EMBCLK Rising Edge EMB[7:0] Hold from EMBCLK Rising Edge Parameter Min 12 12 5 2 Max Units ns ns ns ns Notes
Figure 110. Mailbox 4, Byte 3 Direct Input Timing
t51 EMBCLK t53 EMB[7:0] Valid
t52 t54
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S5935 Pinout and Pin Assignment - 160 PQFP
PTBE3# PTBE2# PTBE1# DQ20 PTBE0# PTRDY# PTATN# EA9 PTBURST# VCC VSS EA8 PTWR PTADR# RDEMPTY DQ21 RDFIFO# WRFULL WRFIFO# EA7 DQ0 DQ1 DQ2 EA6 DQ3 DQ4 DQ5 DQ22 DQ6 VCC VSS EA5 DQ7 BEO# DQ8 DQ23 DQ9 DQ10 DQ11 EA4 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
EQ0 AD23 AD22 AD21 DQ31 AD20 AD19 AD18 EQ1 VSS VCC AD17 DQ30 AD16 C/BE2# FRAME# EQ2 IRDY# TRDY# DEVSEL# EQ3 STOP# LOCK# PERR# DQ29 SERR# PAR C/BE1# EQ4/FWC# VSS VCC AD15 EQ5/FRC# AD14 AD13 AD12 DQ28 AD11 AD10 AD9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
EA10 PTNUM1 PTNUM0 IRQ# DQ19 SYSRST# EWR#/SDA ERD#/SCL EA11 VSS VCC ADR6 DQ18 NC SNV NC EA12 RSVD RST# BPCLK EA13 CLK GNT# REQ# DQ17 AD31 AD30 AD29 EA14/FWE VSS VCC AD28 EA15/FRF AD27 AD26 AD25 DQ16 AD24 C/BE3# IDSEL
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
S5935 (160 PQFP)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
DQ12 DQ13 DQ14 DQ24 DQ15 SELECT# WR# EA3 RD# VCC VSS EA2 ADR2 ADR3 ADR4 DQ25 ADR5 BE1# BE2# EA1 BE3# MODE INTA# EA0 AD0 AD1 AD2 DQ26 AD3 VCC VSS EQ7/AMWEN AD4 AD5 AD6 DQ27 AD7 C/BE0# AD8 EQ6/AMREN
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S5935 Pinout and Pin Assignment - 208 TQFP
VDD VDD VDD PTBE3# PTBE2# PTBE1# DQ20 PTBE0# PTRDY# PTATN# EA9 PTBURST# N/C VSS VSS VSS EA8 PTWR PTADDR# N/C RDEMPTY DQ21 RDFIFO# WRFULL WRFIFO# EA7 DQ0 DQ1 DQ2 EA6 DQ3 DQ4 DQ5 DQ22 DQ6 N/C VDD VSS VSS EA5 N/C DQ7 BE0 DQ8 DQ23 DQ9 DQ10 DQ11 EA4 VSS VSS VDD 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
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VDD VSS VSS EQ0 AD23 AD22 AD21 DQ31 AD20 AD19 AD18 N/C EQ1 VSS VSS VDD VDD AD17 DQ30 AD16 C/BE2# FRAME# EQ2 IRDY# TRDY# DEVSEL# EQ3 STOP# LOCK# PERR# DQ29 SERR# N/C PAR C/BE1# EQ4 VSS VSS VDD VDD AD15 EQ5 AD14 AD13 AD12 DQ28 AD11 AD10 AD9 VDD VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
VDD VSS VSS EA10 PTNUM1 PTNUM0 IRQ# DQ19 STSRST# SDA/EWR SCL/ERD N/C EA11 VSS VSS VDD N/C ADR6 DQ18 NV N/C EA12 RSVD RST# BPCLK EA13 CLK GNT# REQ# DQ17 AD31 AD30 N/C AD29 EA14 VSS VSS VDD N/C AD28 EA15 AD27 AD26 AD25 N/C DQ16 AD24 C/BE3# IDSEL VDD VDD VDD
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
S5935 (208 TQFP)
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
VDD VDD DQ12 DQ13 DQ14 VSS DQ24 DQ15 SELECT# WR# EA3 RD# VDD VSS VSS VSS EA2 ADR2 ADR3 N/C ADR4 DQ25 ADR5 BE1 BE2 EA1 BE3 MODE INTA# EA0 AD0 AD1 AD2 DQ26 AD3 N/C VDD VSS VSS EQ7 N/C AD4 AD5 AD6 DQ27 AD7 C/BE0# AD8 EQ6 VSS VSS VDD
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Data Book
S5935 Numerical Pin Assignment - 160 PQFP
Pin# Signal Type Pin# Signal Type
32
Pin# Signal Type
AD15 EQ5/FRC# AD14 AD13 AD12 DQ28 AD11 AD10 AD9 EQ6/AMREN AD8 C/BE0# AD7 DQ27 AD6 AD5 AD4 EQ7/AMWEN VSS VCC AD3 DQ26 AD2 AD1 AD0 EA0 INTA# MODE BE3# EA1 BE2# BE1# ADR5
t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s V V t/s t/s t/s t/s t/s t/s o/d in in t/s in in in
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
DQ25 ADR4 ADR3 ADR2 EA2 VSS VCC RD# EA3 WR# SELECT# DQ15 DQ24 DQ14 DQ13 DQ12 EA4 DQ11 DQ10 DQ9 DQ23 DQ8 BE0# DQ7 EA5 VSS VCC DQ6 DQ22 DQ5 DQ4 DQ3 EA6
t/s in in in t/s V V in t/s in in t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s in t/s t/s V V t/s t/s t/s t/s t/s t/s
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EQ0 AD23 AD22 AD21 DQ31 AD20 AD19 AD18 EQ1 VSS VCC AD17 DQ30 AD16 C/BE2# FRAME# EQ2 IRDY# TRDY# DEVSEL# EQ3 STOP# LOCK# PERR# DQ29 SERR# PAR C/BE1# EQ4/FWC# VSS VCC
t/s t/s t/s t/s t/s t/s t/s t/s t/s V V t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s in t/s t/s o/d t/s t/s t/s V V
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Pin# Signal Type Pin# Signal Type Pin# Signal Type
98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
DQ2 DQ1 DQ0 EA7 WRFIFO# WRFULL RDFIFO# DQ21 RDEMPTY PTADR# PTWR EA8 VSS VCC PTBURST# EA9 PTATN# PTRDY# PTBE0# DQ20 PTBE1# PTBE2#
t/s t/s t/s t/s in out in t/s out in out t/s V V out out out in out t/s out out
120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141
PTBE3# EA10 PTNUM1 PTNUM0 IRQ# DQ19 SYSRST# EWR#/SDA ERD#/SCL EA11 VSS VCC ADR6 DQ18 NC SNV NC EA12 RSVD RST# BPCLK EA13
out out out out out t/s out t/s out out V V in t/s -- in -- out in in out out
142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
CLK GNT REQ# DQ17 AD31 AD30 AD29 EA14/FWE VSS VCC AD28 EA15/FRF AD27 AD26 AD25 DQ16 AD24 C/BE3# IDSEL
in in out t/s t/s t/s t/s t/s V V t/s t/s t/s t/s t/s t/s t/s t/s in
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Package Physical Dimensions - 160 PQFP Figure 111. S5935 - 160 PQFP Package Drawing
PACKAGE MATERIAL NOTE: Green/RoHS Compliant Package: Lead Finish - MATTE SN.
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Figure 112. S5935 - Marking Drawing
PCI MATCHMAKER S5935UUU XXXXYZZ AAAA
e3
LEGEND (in row order - including symbols):
ROW #1: ROW #2: ROW #3: AMCC Logo (fixed) AMCC Device Part Number (fixed) S5935: Core Part Number (fixed) UUU: Ordering Options (eg. package identifier, lead free, speed grade, ...). Character Length may vary Depending on Options Selected. XXXX: Date Code (variable) Y: Assembly Plant Identifier (variable) ZZ: Traceability Code (variable) ESD Symbol (fixed) AAAA: Assembly Location (Country of Origin) (fixed)
ROW #4: ROW #5: ROW #6:
e3
"e3" Category symbol according to JEDEC: JESD97 standard (fixed). When present, this signifies a lead free package.
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S5935 Numerical Pin Assignment - 208 TQFP
Pin# Signal Type Pin# Signal Type
32
Pin# Signal Type
SERR# N/C PAR C/BE1# EQ4 VSS VSS VDD VDD AD15 EQ5 AD14 AD13 AD12 DQ28 AD11 AD10 AD9 VDD VDD VDD VDD VSS VSS EQ6 AD8 C/BE0# AD7 DQ27 AD6 AD5 AD4 N/C
O --t/s t/s t/s V V V V t/s t/s t/s t/s t/s t/s t/s t/s t/s V V V V V V t/s t/s t/s t/s t/s t/s t/s t/s ---
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
EQ7 VSS VSS VDD N/C AD3 DQ26 AD2 AD1 AD0 EA0 INTA# MODE BE3 EA1 BE2 BE1 ADR5 DQ25 ADR4 N/C ADR3 ADR2 EA2 VSS VSS VSS VDD RD# EA3 WR# SELECT# DQ15
t/s V V V --t/s t/s t/s t/s t/s t/s O I I t/s I I I t/s I --I I t/s V V V V I t/s I I t/s
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VDD VSS VSS EQ0 AD23 AD22 AD21 DQ31 AD20 AD19 AD18 N/C EQ1 VSS VSS VDD VDD AD17 DQ30 AD16 C/BE2# FRAME# EQ2 IRDY# TRDY# DEVSEL# EQ3 STOP# LOCK# PERR# DQ29
V V V t/s t/s t/s t/s t/s t/s t/s t/s --t/s V V V V t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s t/s I t/s t/s
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Pin# Signal Type Pin# Signal Type Pin# Signal Type
98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130
DQ24 VSS DQ14 DQ13 DQ12 VDD VDD VDD VSS VSS EA4 DQ11 DQ10 DQ9 DQ23 DQ8 BE0 DQ7 N/C EA5 VSS VSS VDD N/C DQ6 DQ22 DQ5 DQ4 DQ3 EA6 DQ2 DQ1 DQ0
t/s V t/s t/s t/s V V V V V t/s t/s t/s t/s t/s t/s I t/s --t/s V V V --t/s t/s t/s t/s t/s t/s t/s t/s t/s
131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
EA7 WRFIFO# WRFULL RDFIFO# DQ21 RDEMPTY N/C PTADDR# PTWR EA8 VSS VSS VSS N/C PTBURST# EA9 PTATN# PTRDY# PTBE0# DQ20 PTBE1# PTBE2# PTBE3# VDD VDD VDD VDD VSS VSS EA10 PTNUM1 PTNUM0 IRQ#
t/s I O I t/s O --I O t/s V V V --O t/s O I O t/s O O O V V V V V V O O O O
164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196
DQ19 SYSRST# SDA/EWR SCL/ERD N/C EA11 VSS VSS VDD N/C ADR6 DQ18 NV N/C EA12 RSVD RST# BPCLK EA13 CLK GNT# REQ# DQ17 AD31 AD30 N/C AD29 EA14 VSS VSS VDD N/C AD28
t/s O O O --O V V V --I t/s I --O I I t/s O I I O t/s t/s t/s --t/s O V V V --t/s
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Pin# Signal Type Pin# Signal Type Pin# Signal Type
197 198 199 200 201
EA15 AD27 AD26 AD25 N/C
O t/s t/s t/s ---
202 203 204 205 206
DQ16 AD24 C/BE3# IDSEL VDD
t/s t/s t/s I V
207 208
VDD VDD
V V
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Figure 113. Package Physical Dimension - 208 TQFP
PACKAGE MATERIAL NOTE: Standard Package: Lead Composition - 75/25 to 90/10 Sn/Pb.
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DOCUMENT REVISION HISTORY
Revision Date Description
1.01
06/23/06
- Pg. 197, Added Package Drawing - Pg. 198, Added Marking Drawing - Pg. 202, Updated Package Drawing - Pg. 204, Updated Ordering Information
AMCC Confidential and Proprietary
DS1527
203
S5935 - PCI Product
Revision 1.02 - June 27, 2006
Data Book
Ordering Information
Prefix Device Package Type QF - 160 PQFP QRC - 160 PQFP Green / RoHS Compliant Package TFC - 208 TQFP
S - Integrated Circuit
5935
X Prefix
XXXX Device
XXXX Package Type
Example: S5935QRC
Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 -- (800) 755-2622 -- Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products, its data sheets, or related documentation without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC's Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (c) 2006 Applied Micro Circuits Corporation.
204
DS1527
AMCC Confidential and Proprietary

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